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11. 发明申请

US20080271133A1 Authenticating a Requestor Without Providing a Key 失效
标题翻译：验证请求者而不提供密钥
公开(公告)号：US20080271133A1
公开(公告)日：2008-10-30
申请号：US12168201
申请日：2008-07-07
申请人： Thomas M. Brey , Giles R. Frazier , Gregory F. Pfister , William J. Rooney
发明人： Thomas M. Brey , Giles R. Frazier , Gregory F. Pfister , William J. Rooney
IPC分类号： H04L9/32
CPC分类号： H04L63/06 , G06F2221/2105 , G06F2221/2129 , H04L29/12009 , H04L61/00 , H04L63/08 , H04L67/1097 , H04L69/329
摘要： A method for authenticating a requesting entity in a communications environment. In an exemplary embodiment, the method includes determining a client identification of a client node associated with the requesting entity, and determining whether the requesting entity associated with the client node is acting in a supervisor capacity. A key to the requesting entity is returned from a resource provider node upon determining that the client identification of the client node indicates that the client node is permitted to access one or more resources of the provider node, and that the client node is acting in a supervisor capacity.
摘要翻译：一种用于在通信环境中认证请求实体的方法。在示例性实施例中，该方法包括确定与请求实体相关联的客户端节点的客户端标识，以及确定与客户端节点相关联的请求实体是否以监督能力行事。在确定客户端节点的客户端标识指示客户端节点被允许访问提供商节点的一个或多个资源，并且客户端节点正在执行时，从资源提供商节点返回请求实体的密钥主管能力。

12. 发明授权

US07437447B2 Method and system for authenticating a requestor without providing a key 有权
标题翻译：用于在不提供密钥的情况下认证请求者的方法和系统
公开(公告)号：US07437447B2
公开(公告)日：2008-10-14
申请号：US10987280
申请日：2004-11-12
申请人： Thomas M. Brey , Giles R. Frazier , Gregory F. Pfister , William J. Rooney
发明人： Thomas M. Brey , Giles R. Frazier , Gregory F. Pfister , William J. Rooney
IPC分类号： G06F15/16
CPC分类号： H04L63/06 , G06F2221/2105 , G06F2221/2129 , H04L29/12009 , H04L61/00 , H04L63/08 , H04L67/1097 , H04L69/329
摘要： A method for authenticating a requesting entity in a communications environment. In an exemplary embodiment, the method includes determining a client identification of a client node associated with the requesting entity, and determining whether the requesting entity associated with the client node is acting in a supervisor capacity. A key to the requesting entity is returned from a resource provider node upon determining that the client identification of the client node indicates that the client node is permitted to access one or more resources of the provider node, and that the client node is acting in a supervisor capacity.
摘要翻译：一种用于在通信环境中认证请求实体的方法。在示例性实施例中，该方法包括确定与请求实体相关联的客户端节点的客户端标识，以及确定与客户端节点相关联的请求实体是否以监督能力行事。在确定客户端节点的客户端标识指示客户端节点被允许访问提供商节点的一个或多个资源，并且客户端节点正在执行时，从资源提供商节点返回请求实体的密钥主管能力。

13. 发明申请

US20080168258A1 Method and Apparatus For Selecting the Architecture Level to Which a Processor Appears to Conform 有权
标题翻译：用于选择处理器符合的架构级别的方法和设备
公开(公告)号：US20080168258A1
公开(公告)日：2008-07-10
申请号：US11621393
申请日：2007-01-09
申请人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
发明人： William J. Armstrong , Richard L. Arndt , Michael J. Corrigan , Giles R. Frazier , Timothy R. Marchini , Cathy May , Naresh Nayar , John T. O'Quin
IPC分类号： G06F15/76 , G06F9/30
CPC分类号： G06F9/30101 , G06F9/30181 , G06F9/468
摘要： A method and system for selecting the architecture level to which a processor appears to conform within a computing environment when executing specific logical partitions or programs and performing migration among different levels of processor architecture. The method utilizes a “processor compatibility register” (PCR) that controls the level of the architecture that the processor appears to support. In one embodiment, the PCR is accessible only to super-privileged software. The super-privileged software sets bits in the PCR that specify the architecture level that the processor is to appear to support so that when the program runs on the processor, the processor behaves in accordance with the architecture level for which the program was designed.
摘要翻译：一种用于在执行特定逻辑分区或程序并且在不同级别的处理器架构之间执行迁移时，选择处理器在计算环境内符合的架构级别的方法和系统。该方法利用“处理器兼容性寄存器”（PCR）来控制处理器似乎支持的架构级别。在一个实施方案中，PCR仅可用于超特权软件。超级特权软件设置PCR中的位，指定处理器将要支持的架构级别，以便当程序在处理器上运行时，处理器的行为与程序设计的架构级别相符。

14. 发明授权

US06785241B1 Method for pacing buffered data transfers over a network such as fibre channel 有权
标题翻译：用于通过诸如光纤通道的网络对缓冲数据传送进行起搏的方法
公开(公告)号：US06785241B1
公开(公告)日：2004-08-31
申请号：US09452992
申请日：1999-12-02
申请人： Tan Lu , Daniel F. Casper , David F. Craddock , Robert J. Dugan , Giles R. Frazier
发明人： Tan Lu , Daniel F. Casper , David F. Craddock , Robert J. Dugan , Giles R. Frazier
IPC分类号： H04L1256
CPC分类号： H04L1/1835 , H04L1/16 , H04L1/1874
摘要： The present invention provides a method for managing transmissions to a remote node having a buffer memory for receiving the transmitted packets and means for acknowledging the receipt of the packets. The method provides for a sender to maintain a sense of the availability of buffer memory even when acknowledging messages are lost with minimal impact on performance.
摘要翻译：本发明提供了一种用于管理向具有用于接收所发送的分组的缓冲存储器的远程节点的传输的方法和用于确认分组的接收的装置。该方法提供了发送者即使在确认消息丢失而对性能影响最小的情况下也能够保持缓冲存储器的可用性感。

15. 发明授权

US06609165B1 Method and apparatus for using fibre channel extended link service commands in a point-to-point configuration 有权
标题翻译：在点对点配置中使用光纤通道扩展链路服务命令的方法和装置
公开(公告)号：US06609165B1
公开(公告)日：2003-08-19
申请号：US09407046
申请日：1999-09-27
申请人： Giles R. Frazier
发明人： Giles R. Frazier
IPC分类号： G06F1314
CPC分类号： H04L12/437 , H04L49/357
摘要： The present invention provides fibre channel networks the ability to use extended link service commands, previously confined to networks including a fabric controller, in a direct attach, point-to-point configuration.
摘要翻译：本发明提供光纤通道网络能够以直接连接点对点配置使用先前局限于包括结构控制器的网络的扩展链路服务命令。

16. 发明授权

US5544333A System for assigning and identifying devices on bus within predetermined period of time without requiring host to do the assignment 失效
标题翻译：用于在预定时间段内在总线上分配和识别设备的系统，而不需要主机进行分配
公开(公告)号：US5544333A
公开(公告)日：1996-08-06
申请号：US380473
申请日：1995-01-30
申请人： Giles R. Frazier , Gary Y. Tsao
发明人： Giles R. Frazier , Gary Y. Tsao
IPC分类号： G06F12/06 , G06F15/177 , G06F13/38
CPC分类号： G06F9/4411 , G06F12/0669 , G06F15/177
摘要： In a computer system having multiple devices on a bus, a method for a first device on the bus to designate its own identifier including the steps of the first device transmitting on the bus a request for a device with a desired identifier to respond, determining that no device on the bus responds to the request, and upon such determination, designating the desired identifier to identify the first device to at least one of the multiple devices on the bus. In addition, in a computer system having multiple devices on a bus, a first device including apparatus for transmitting on the bus a request for a device with a desired identifier to respond, apparatus for determining that no device on the bus responds to the request, and apparatus for, upon such determination, designating the desired identifier to identify at least one of the first device to the multiple devices on the bus.
摘要翻译：在具有总线上的多个设备的计算机系统中，一种用于总线上的第一设备的方法来指定其自己的标识符，包括第一设备在总线上发送对具有所需标识符的设备的请求进行响应的步骤，确定总线上的任何设备都不响应该请求，并且在这样的确定时，指定所需的标识符以将总线上的多个设备中的至少一个设备识别出第一设备。此外，在具有总线上的多个设备的计算机系统中，第一设备包括用于在总线上发送对具有所需标识符进行响应的设备的请求的设备，用于确定总线上的设备不响应该请求的设备，以及用于在所述确定时指定所述期望标识符以将所述第一设备中的至少一个识别到所述总线上的所述多个设备的装置。

17. 发明授权

US4222080A Velocity tolerant decoding technique 失效
标题翻译：速度容错解码技术
公开(公告)号：US4222080A
公开(公告)日：1980-09-09
申请号：US971969
申请日：1978-12-21
申请人： Giles R. Frazier
发明人： Giles R. Frazier
IPC分类号： H03M5/04 , G11B20/14 , H03M5/12 , H04L25/49 , G11B5/09
CPC分类号： G11B20/1423 , G11B20/1419
摘要： A decoding technique applicable to binary data encoded by phase encoding (PE), frequency modulation (FM), or modified frequency modulation (MFM). Resynchronization of the decoding clocking circuitry occurs upon every flux transition, rather than at less than all flux transitions, such as only at each data flux transition in the case of phase encoding. The technique provides substantially greater velocity tolerance than previous techniques for decoding codes encoded in this manner.
摘要翻译：适用于通过相位编码（PE），频率调制（FM）或修改频率调制（MFM）编码的二进制数据的解码技术。解码时钟电路的再同步发生在每个通量转换上，而不是在小于所有通量转换处，例如仅在相位编码的情况下的每个数据通量转换时才发生。该技术提供比以前用于以这种方式编码的代码的技术更大的速度容差。

18. 发明授权

US09342432B2 Hardware performance-monitoring facility usage after context swaps 有权
标题翻译：情景交换后的硬件性能监控设备使用情况
公开(公告)号：US09342432B2
公开(公告)日：2016-05-17
申请号：US13313557
申请日：2011-12-07
申请人： Giles R. Frazier , Brian R. Mestan
发明人： Giles R. Frazier , Brian R. Mestan
IPC分类号： G06F11/34
CPC分类号： G06F11/348 , G06F2201/865
摘要： A performance monitoring technique provides task-switch immune operation without requiring storage and retrieval of the performance monitor state when a task switch occurs and provides accurate performance monitoring information. When a hypervisor signals that a task is being resumed and the application privilege level has been entered, it provides an indication, which starts a delay timer. The delay timer is resettable in case a predetermined time period has not elapsed when the next task switch occurs. After the delay timer expires, analysis of the performance monitor measurements is resumed, which prevents an initial state, a state due to execution of the operating system or hypervisor, or a state remaining from a previous task from corrupting the performance monitoring results. The performance monitor may be or include an execution trace unit that collects branch information in a current program execution trace.
摘要翻译：性能监控技术提供任务切换免疫操作，而不需要在任务切换发生时存储和检索性能监视状态，并提供准确的性能监视信息。当管理程序发出信号指示正在恢复任务并且已经输入了应用程序权限级别时，它提供指示，其启动延迟定时器。在发生下一任务切换的情况下，在没有经过预定时间段的情况下，可以将延迟定时器复位。在延迟定时器到期后，恢复对性能监视器测量的分析，这阻止了初始状态，由于执行操作系统或管理程序的状态，或者从前一任务中剩余的状态破坏性能监视结果。性能监视器可以是或包括在当前程序执行跟踪中收集分支信息的执行跟踪单元。

19. 发明授权

US09069598B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
标题翻译：提供逻辑分支与反映独家使用处理器核心的硬件线程特定信息
公开(公告)号：US09069598B2
公开(公告)日：2015-06-30
申请号：US13345002
申请日：2012-01-06
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.
摘要翻译：用于模拟在多个逻辑分区（LPAR）中独占使用处理器核心的技术包括提供响应于LPAR的访问请求的硬件线程依赖状态信息，所述LPAR反映了LPAR访问硬件线程相关的独占使用处理器信息。如果请求者是在低于管理程序权限级别的特权级别下执行的程序，则转换响应于访问请求而返回的信息，使得每个逻辑分区将处理器视为处理器的独占使用。这些技术可以由处理器核心内的逻辑电路块来实现，其将硬件线程特定信息转换为硬件线程特定信息的逻辑表示，或者可以通过将访问陷阱的中断处理程序的程序指令执行物理寄存器包含信息。

20. 发明授权

US08990816B2 Providing logical partions with hardware-thread specific information reflective of exclusive use of a processor core 有权
公开(公告)号：US08990816B2
公开(公告)日：2015-03-24
申请号：US13452745
申请日：2012-04-20
申请人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
发明人： Giles R. Frazier , Bruce Mealy , Naresh Nayar
IPC分类号： G06F9/52 , G06F9/455 , G06F9/38
CPC分类号： G06F21/6218 , G06F9/3012 , G06F9/3851 , G06F9/45541 , G06F9/45558 , G06F2009/45587
摘要： Techniques for simulating exclusive use of a processor core amongst multiple logical partitions (LPARs) include providing hardware thread-dependent status information in response to access requests by the LPARs that is reflective of exclusive use of the processor by the LPAR accessing the hardware thread-dependent information. The information returned in response to the access requests is transformed if the requestor is a program executing at a privilege level lower than the hypervisor privilege level, so that each logical partition views the processor as though it has exclusive use of the processor. The techniques may be implemented by a logical circuit block within the processor core that transforms the hardware thread-specific information to a logical representation of the hardware thread-specific information or the transformation may be performed by program instructions of an interrupt handler that traps access to the physical register containing the information.

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