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11. 发明申请

US20110180931A1 ROBUST HIGH ASPECT RATIO SEMICONDUCTOR DEVICE 有权
标题翻译：稳定的高倍率半导体器件
公开(公告)号：US20110180931A1
公开(公告)日：2011-07-28
申请号：US13121268
申请日：2009-09-24
申请人： Freddy Roozeboom , Martijn Goossens , Willen Frederik Adrianus Besling , Nynke Verhaegh
发明人： Freddy Roozeboom , Martijn Goossens , Willen Frederik Adrianus Besling , Nynke Verhaegh
IPC分类号： H01L23/48 , G03F1/00
CPC分类号： H01L29/41 , B81B3/007 , B81B2201/06 , B81C1/00619 , B81C2201/0112 , B81C2201/0132 , H01L28/91
摘要： The invention relates to an semi-conductor device comprising a first surface and neighboring first and second electric elements arranged on the first surface, in which each of the first and second elements extends from the first surface in a first direction, the first element having a cross section substantially perpendicular to the first direction and a sidewall surface extending at least partially in the first direction, wherein the sidewall surface comprises a first section and a second section adjoining the first section along a line extending substantially parallel to the first direction, wherein the first and second sections are placed at an angle with respect to each other for providing an inner corner wherein the sidewall surface at the inner corner is, at least partially, arranged at a constant distance R from a facing part of the second element for providing a mechanical reinforcement structure at the inner corner.
摘要翻译：本发明涉及一种半导体器件，其包括第一表面和布置在第一表面上的相邻的第一和第二电气元件，其中第一和第二元件中的每个元件在第一方向上从第一表面延伸，第一元件具有基本上垂直于第一方向的横截面和至少部分地沿第一方向延伸的侧壁表面，其中侧壁表面包括沿着基本上平行于第一方向延伸的线邻接第一部分的第一部分和第二部分，其中，第一和第二部分相对于彼此以一定角度放置以提供内角，其中内角处的侧壁表面至少部分地布置成距离第二元件的面对部分恒定的距离R，以提供机械加强结构在内角。

12. 发明申请

US20100230787A1 ELECTRIC DEVICE COMPRISING AN IMPROVED ELECTRODE 有权
标题翻译：包含改进电极的电气设备
公开(公告)号：US20100230787A1
公开(公告)日：2010-09-16
申请号：US12299325
申请日：2007-04-30
申请人： Lionel Guiraud , Francois Lecornec , Johan H. Klootwijk , Freddy Roozeboom , David D. R. Chevrie
发明人： Lionel Guiraud , Francois Lecornec , Johan H. Klootwijk , Freddy Roozeboom , David D. R. Chevrie
IPC分类号： H01L27/08
CPC分类号： H01L27/0805 , H01L27/10817 , H01L27/10829 , H01L27/10852 , H01L27/10861 , H01L28/40 , H01L28/82 , H01L28/90 , H01L29/6609 , H01L29/66181 , H01L29/861
摘要： The invention relates to an electric device including an electric element, the electric element comprising a first electrode (104) having a first surface (106) and a pillar (108), the pillar extending from the first surface in a first direction (110), the pillar having a length measured from the first surface parallel to the first direction, the pillar having a cross section (116) perpendicular to the first direction and the pillar having a sidewall surface (120) enclosing the pillar and extending in the first direction, characterized in—that, the pillar comprises any one of a score (124) and protrusion (122) extending along at least part of the length of the pillar for giving the pillar (108) improved mechanical stability. The electrode allows electrical elements such as capacitors, energy storage devices or diodes to be made with improved properties in a cost effective way.
摘要翻译：本发明涉及一种包括电气元件的电气设备，电气元件包括具有第一表面（106）和柱（108）的第一电极（104），该柱从第一表面沿第一方向（110）延伸，，所述柱具有从所述第一表面平行于所述第一方向测量的长度，所述柱具有垂直于所述第一方向的横截面（116），所述柱具有封闭所述柱并且沿所述第一方向延伸的侧壁表面（120）其特征在于，所述支柱包括沿柱的长度的至少一部分延伸的刻痕（124）和突起（122）中的任何一个，以提供支柱（108）改善的机械稳定性。电极允许以成本有效的方式制造诸如电容器，储能装置或二极管的电气元件，具有改进的性能。

13. 发明授权

US07772800B2 Energy system comprising an electrochemical energy source 失效
标题翻译：能量系统包括电化学能源
公开(公告)号：US07772800B2
公开(公告)日：2010-08-10
申请号：US11719867
申请日：2005-11-25
申请人： Freddy Roozeboom , Peter Notten
发明人： Freddy Roozeboom , Peter Notten
IPC分类号： H01M10/46
CPC分类号： H01M10/465 , H01M6/40 , H01M10/0436 , H01M10/0525 , H01M10/0562 , H01M10/058 , Y02E60/122 , Y02P70/54 , Y10T29/49115
摘要： The invention relates to an energy system comprising an electrochemical energy source, wherein said electrochemical energy source comprises at least one assembly of a first electrode, a second electrode, and an intermediate solid-state electrolyte separating said first electrode and said second electrode. The invention also relates to an electronic module provided with such an energy system. The invention further relates to an electronic device provided with such an energy system. Moreover, the invention relates to a method of manufacturing of such an energy system.
摘要翻译：本发明涉及包含电化学能源的能量系统，其中所述电化学能源包括分离所述第一电极和所述第二电极的第一电极，第二电极和中间固态电解质的至少一个组件。本发明还涉及一种具有这种能量系统的电子模块。本发明还涉及一种具有这种能量系统的电子设备。此外，本发明涉及这种能量系统的制造方法。

14. 发明申请

US20100117612A1 DC-TO-DC CONVERTER COMPRISING A RECONFIGURABLE CAPACITOR UNIT 有权
标题翻译：包含可重构电容单元的DC-DC转换器
公开(公告)号：US20100117612A1
公开(公告)日：2010-05-13
申请号：US12597308
申请日：2008-05-08
申请人： Johan H. Klootwijk , Hendrik J. Bergveld , Freddy Roozeboom , Derk Reefman , Jaap Ruigrok
发明人： Johan H. Klootwijk , Hendrik J. Bergveld , Freddy Roozeboom , Derk Reefman , Jaap Ruigrok
IPC分类号： H02M3/07
CPC分类号： H01L27/0805 , H02M3/07
摘要： The present invention relates to a configurable trench multi-capacitor device comprising a trench in a semiconductor substrate. The trench has a lateral extension exceeding 10 micrometer and a trench filling includes a number of at least four electrically conductive capacitor-electrode layers. A switching unit is provided that comprises a plurality of switching elements electrically interconnected between different capacitor-electrode layers of the trench filling. A control unit is connected with the switching unit and configured to generate and provide to the switching unit respective control signals for forming a respective one of a plurality of multi-capacitor configurations using the capacitor-electrode layers of the trench filling.
摘要翻译：本发明涉及一种包括半导体衬底中的沟槽的可配置沟槽多电容器器件。沟槽的横向延伸超过10微米，沟槽填充物包括多个至少四个导电电容器电极层。提供一种开关单元，其包括在沟槽填充物的不同电容器 - 电极层之间电连接的多个开关元件。控制单元与开关单元连接，并且被配置为使用沟槽填充的电容器电极层，生成并向开关单元提供各自的控制信号，以形成多个多电容器配置中的相应一个。

15. 发明授权

US07704881B2 Producing a covered through substrate via using a temporary cap layer 有权
标题翻译：通过使用临时盖层生产覆盖的基板
公开(公告)号：US07704881B2
公开(公告)日：2010-04-27
申请号：US12092605
申请日：2006-11-03
申请人： Johan H. Klootwijk , Antonius L. A. M. Kemmeren , Ronald Dekker , Eric Cornelis Egbertus Van Grunsven , Freddy Roozeboom
发明人： Johan H. Klootwijk , Antonius L. A. M. Kemmeren , Ronald Dekker , Eric Cornelis Egbertus Van Grunsven , Freddy Roozeboom
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/764 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to a method for producing a substrate with at least one covered via that electrically and preferably also thermally connects a first substrate side with an opposite second substrate side. The processing involves forming a trench on a the first substrate side remains and covering the trench with a permanent layer on top of a temporary, sacrificial cap-layer, which is decomposed in a thermal process step. The method of the invention provides alternative ways to remove decomposition products of the sacrificial cap-layer material without remaining traces or contamination even in the presence of the permanent layer. This is, according to a first aspect of the invention, achieved by providing the substrate trench with an overcoat layer that has holes. The holes in the overcoat layer leave room for the removal of the decomposition products of the cap-layer material. According to the second aspect of the invention, opening the covered trench from the second substrate side and allowing the cap-layer material to be removed through that opening provides a solution. Both methods of the present invention are based on the common idea of using a temporary cap-layer even in a situation where the substrate opening is permanently covered before the removal of the temporary cap-layer.
摘要翻译：本发明涉及一种制造具有至少一个覆盖通孔的基板的方法，所述至少一个覆盖通孔电连接并优选地将第一基板侧与相对的第二基板侧热连接。所述处理涉及在第一基板侧上形成沟槽，并在热处理步骤中分解的临时牺牲盖层的顶部上保留并覆盖具有永久层的沟槽。本发明的方法提供了即使在存在永久层的情况下除去牺牲帽层材料的分解产物而不留下痕迹或污染物的替代方法。根据本发明的第一方面，这是通过为基底沟槽提供具有孔的外涂层而实现的。外涂层中的孔留下去除盖层材料的分解产物的空间。根据本发明的第二方面，从第二基板侧打开被覆盖的沟槽并且允许通过该开口去除盖层材料提供了一种解决方案。本发明的两种方法都是基于即使在去除临时盖层之前基材开口被永久地覆盖的情况下使用临时盖层的常见思想。

16. 发明申请

US20100013060A1 METHOD OF FORMING A CONDUCTIVE TRENCH IN A SILICON WAFER AND SILICON WAFER COMPRISING SUCH TRENCH 审中-公开
标题翻译：在硅砂中形成导电铁的方法和包含这种铁素体的硅膜
公开(公告)号：US20100013060A1
公开(公告)日：2010-01-21
申请号：US12507269
申请日：2009-07-22
申请人： Yann Pierre Roger Lamy , Freddy Roozeboom , Fredricus van den Heuvel
发明人： Yann Pierre Roger Lamy , Freddy Roozeboom , Fredricus van den Heuvel
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a conductive trench such as a through-silicon-via in a silicon wafer is disclosed. The method includes depositing a mask over a wafer surface; patterning the mask to expose a portion of the wafer; exposing the wafer to a first etching step in which a first portion of the trench is formed; exposing the wafer to an second etching step in which a tapered second portion of the trench is formed, where the first portion has a continuously non-increasing width from the wafer surface to the second portion; and filling the trench with a conductive material. A silicon wafer including such a conductive trench is also disclosed.
摘要翻译：公开了一种在硅晶片中形成例如硅通孔的导电沟槽的方法。该方法包括在晶片表面上沉积掩模; 图案化掩模以暴露晶片的一部分; 将晶片暴露于其中形成沟槽的第一部分的第一蚀刻步骤; 将晶片曝光到第二蚀刻步骤，其中形成沟槽的锥形第二部分，其中第一部分具有从晶片表面到第二部分的连续不增加的宽度; 并用导电材料填充沟槽。还公开了包括这种导电沟槽的硅晶片。

17. 发明授权

US06790690B2 Method of manufacturing a display device 失效
标题翻译：制造显示装置的方法
公开(公告)号：US06790690B2
公开(公告)日：2004-09-14
申请号：US10052342
申请日：2002-01-18
申请人： Herbert Lifka , Freddy Roozeboom , Rene Johan Gerrit Elfrink , Mark Thomas Johnson
发明人： Herbert Lifka , Freddy Roozeboom , Rene Johan Gerrit Elfrink , Mark Thomas Johnson
IPC分类号： H01L2100
CPC分类号： G02F1/1362 , H01L25/50 , H01L27/15 , H01L27/32 , H01L2924/0002 , H01L2924/00
摘要： ICs (20) are nearly separated from the semiconductor substrate (10) on/in which they are formed. Subsequently, the substrate is positioned upside down on a substrate (carrier) (3) which is provided with glue (21) at the location of a crystal. After attachment of the crystal to the carrier, the semiconductor substrate is removed and the crystal remains attached to the carrier e.g. at the crossing of rows and columns. The separate crystals may contain TFTs (simple AM addressing) but also more complicated electronics (address of pixel in memory+identification).
摘要翻译： IC（20）在形成它们之后几乎与半导体衬底（10）分离。随后，将基板上下放置在在晶体位置处设置有胶水（21）的基板（载体）（3）上。在将晶体附着到载体之后，去除半导体衬底，并且晶体保持附着到载体上。在行和列的交叉处。单独的晶体可能包含TFT（简单的AM寻址），也可能是更复杂的电子元件（存储器中的像素地址+识别）。

18. 发明授权

US08563990B2 Electronic device and method of manufacturing an electronic device 有权
标题翻译：电子设备及其制造方法
公开(公告)号：US08563990B2
公开(公告)日：2013-10-22
申请号：US12419900
申请日：2009-04-07
申请人： Freddy Roozeboom , Herbert Lifka , Frederik Vanhelmont , Wouter Dekkers
发明人： Freddy Roozeboom , Herbert Lifka , Frederik Vanhelmont , Wouter Dekkers
IPC分类号： H01L33/00
CPC分类号： H01L27/288 , G02B6/43 , H01L24/73 , H01L25/0657 , H01L25/167 , H01L27/32 , H01L31/0203 , H01L2224/48091 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06575 , H01L2924/01046 , H01L2924/10253 , H01L2924/12041 , H01L2924/12042 , H01L2924/12044 , H01L2924/1305 , H01L2924/00014 , H01L2924/00
摘要： An electronic device comprising at least one die stack having at least a first die (D1) comprising a first array of light emitting units (OLED) for emitting light, a second layer (D2) comprising a second array of via holes (VH) and a third die (D3) comprising a third array of light detecting units (PD) for detecting light from the first array of light emitting units (OELD) is provided. The second layer (D2) is arranged between the first die (D1) and the third die (D3). The first, second and third array are aligned such that light emitted from the first array of light emitting units (OLED) passed through the second array of via holes (VH) and is detected by the third array of light detecting units (PD). The first array of light emitting units and/or the third array of light detecting units are manufactured based on standard semiconductor manufacturing processes.
摘要翻译：一种电子装置，包括至少一个具有至少一个第一管芯（D1）的管芯堆叠，所述第一管芯（D1）包括用于发射光的第一发光单元阵列（OLED），包括通孔（VH）的第二阵列的第二层（D2）提供了包括用于检测来自第一阵列的发光单元（OELD）的光的第三阵列的光检测单元（PD）的第三裸片（D3）。第二层（D2）布置在第一管芯（D1）和第三管芯（D3）之间。对准第一，第二和第三阵列，使得从第一阵列的发光单元（OLED）发射的光穿过第二阵列的通孔（VH）并被第三阵列的光检测单元（PD）检测。基于标准半导体制造工艺制造第一阵列的发光单元和/或第三阵列的光检测单元。

19. 发明申请

US20120133047A1 Method of Plating Through Wafer Vias in a Wafer for 3D Packaging 有权
标题翻译：通过晶片通孔进行3D封装的方法
公开(公告)号：US20120133047A1
公开(公告)日：2012-05-31
申请号：US13120988
申请日：2009-09-29
申请人： Willem Frederik Adrianus Besling , Freddy Roozeboom , Yann Pierre Roger Lamy
发明人： Willem Frederik Adrianus Besling , Freddy Roozeboom , Yann Pierre Roger Lamy
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2224/05009 , H01L2224/06181 , H01L2924/1461 , H01L2924/00
摘要： Therefore, a method of plating wafer via holes in a wafer is provided. A substrate (200) having a first and second side and a plurality of wafer via holes (210) is provided. Each via hole comprises a first and second end extending between the first and second side. A first seed layer (220) is deposited on the first side of the 5 wafer (200). A foil (250) is applied on the first seed layer (220) of the wafer closing the first ends of the plurality of wafer via holes (210). The second side of the wafer (200) is electro-chemically plated and the foil (250) is removed.
摘要翻译：因此，提供了在晶片中电镀晶片通孔的方法。提供了具有第一和第二侧面以及多个晶片通孔（210）的基板（200）。每个通孔包括在第一和第二侧之间延伸的第一和第二端。第一种子层（220）沉积在5晶片（200）的第一侧上。箔片（250）被施加在封闭多个晶片通孔（210）的第一端的晶片的第一晶种层（220）上。晶片（200）的第二面被电化学镀，并且去除箔（250）。

20. 发明申请

US20110128111A1 PLANAR, MONOLITHICALLY INTEGRATED COIL 有权
标题翻译：平面，单层集成线圈
公开(公告)号：US20110128111A1
公开(公告)日：2011-06-02
申请号：US13002152
申请日：2009-06-30
申请人： Freddy Roozeboom , Derk Reefman , Johan Hendrik Klootwijk , Lukas Frederik Tiemeijer , Jaap Ruigrok
发明人： Freddy Roozeboom , Derk Reefman , Johan Hendrik Klootwijk , Lukas Frederik Tiemeijer , Jaap Ruigrok
IPC分类号： H01F27/36 , H01F5/00
CPC分类号： H01F17/0006 , H01F27/365 , H01F2017/0066 , H01F2017/008
摘要： The present invention provides a means to integrate planar coils on silicon, while providing a high inductance. This high inductance is achieved through a special back- and front sided shielding of a material. In many applications, high-value inductors are a necessity. In particular, this holds for applications in power management. In these applications, the inductors are at least 5 of the order of 1 μH, and must have an equivalent series resistance of less than 0.1 Ω. For this reason, those inductors are always bulky components, of a typical size of 2×2×1 mm 3, which make a fully integrated solution impossible. On the other hand, integrated inductors, which can monolithically be integrated, do exist. However, these inductors suffer either from low inductance values, or 10 very-high DC resistance values.
摘要翻译：本发明提供了一种在硅上集成平面线圈同时提供高电感的方法。这种高电感通过材料的特殊背面和前面屏蔽来实现。在许多应用中，高值感应器是必需的。特别是适用于电源管理的应用。在这些应用中，电感器的电阻值至少为1μH，必须具有小于0.1Ω的等效串联电阻。因此，这些电感器通常是典型尺寸为2×2×1mm 3的体积较大的部件，这使得完全集成的解决方案不可能。另一方面，确实存在可以整体集成的集成电感器。然而，这些电感器受到低电感值或10个非常高的直流电阻值的影响。

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