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11. 发明授权

US5524255A Method and apparatus for accessing global registers in a multiprocessor system 失效
标题翻译：用于在多处理器系统中访问全局寄存器的方法和装置
公开(公告)号：US5524255A
公开(公告)日：1996-06-04
申请号：US379123
申请日：1995-01-27
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80 , G06F15/163
CPC分类号： G06F9/3004 , G06F15/17 , G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30043 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A global register system provides communication and coordination among a plurality of processors sharing a common memory in a multiprocessor system which access one or more registers within a shared resource circuit that is separate from the common memory and is symmetrically accessible by the plurality of processors in the multiprocessor system. The global register system is accessed by direct addresses determined by the processor from a previously assigned indirect address and an instruction accessing the data stored in global registers. Arithmetic or logic operation on a data value stored in a selected one of the registers are performed by the global register system independent from the processors or the common memory in order to modify the data value in the selected global register as part of an atomic operation performed in response to a single read-and-modify instruction received from one of the processors.
摘要翻译：全局注册系统提供在多处理器系统中共享公共存储器的多个处理器之间的通信和协调，多处理器系统访问共享资源电路内的一个或多个与公共存储器分离的寄存器，并且可由多个处理器对称地访问多处理器系统全局寄存器系统由处理器从先前分配的间接地址确定的直接地址和访问存储在全局寄存器中的数据的指令访问。存储在所选择的一个寄存器中的数据值的算术或逻辑运算由独立于处理器或公共存储器的全局寄存器系统执行，以便修改所选择的全局寄存器中的数据值，作为执行的原子操作的一部分响应于从一个处理器接收的单个读取和修改指令。

12. 发明授权

US5208914A Method and apparatus for non-sequential resource access 失效
标题翻译：用于非顺序资源访问的方法和装置
公开(公告)号：US5208914A
公开(公告)日：1993-05-04
申请号：US535786
申请日：1990-06-11
申请人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
发明人： Jimmie R. Wilson , Douglas R. Beard , Steve S. Chen , Roger E. Eckert , Richard E. Hessel , Andrew E. Phelps , Alexander A. Silbey , Brian D. Vanderwarn
IPC分类号： G06F9/46 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F12/00 , G06F15/16 , G06F15/173 , G06F15/177 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/30094 , G06F9/3013 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3855 , G06F9/3857
摘要： A method and apparatus for non-sequential access to shared resources in a multiple requestor system uses a variety of tags to effectively re-order the data at its destination. In simplest form, the tag directs switching logic to where in a buffer to locate another tag for direction information or where in a buffer or processor (register) to put the response associated with the tag. For example, loading data from memory requires that the requestor provide a request signal, an address, and a request tag. The request signal validates the address and request tag. The address specifies the location of the requested data in memory. The request tag specifies where to put the data when it is returned to the processor. The switching logic for the requestor includes a tag queue for storing the request tags associated with the resource requests, logic means for associating the respective request tag from the tag queue with a resource response, and means for returning the resource response and respective request tag to the requestor. The switching logic associated with the shared resource includes switching means to route the request into and out of the shared resource, control logic to correctly route the request, logic to handle multiple decision requests, and logic to store or retrieve the ultimate data entity being requested.
摘要翻译：用于在多请求者系统中非顺序访问共享资源的方法和装置使用各种标签来有效地重新排序其目的地的数据。以最简单的形式，标签将切换逻辑引导到缓冲器中的哪个位置，以定位用于方向信息的另一个标签，或者在缓冲器或处理器（寄存器）中放置与标签相关联的响应的位置。例如，从存储器加载数据要求请求者提供请求信号，地址和请求标签。请求信号验证地址和请求标签。该地址指定所请求的数据在内存中的位置。请求标签指定在将数据返回到处理器时放置数据的位置。用于请求者的切换逻辑包括用于存储与资源请求相关联的请求标签的标记队列，用于将来自标签队列的相应请求标签与资源响应相关联的逻辑装置，以及用于将资源响应和相应请求标签返回到请求者。与共享资源相关联的切换逻辑包括将请求路由到共享资源和从共享资源引出的切换装置，控制逻辑以正确路由请求，处理多个决策请求的逻辑以及存储或检索被请求的最终数据实体的逻辑。

13. 发明授权

US4953079A Cache memory address modifier for dynamic alteration of cache block fetch sequence 失效
标题翻译：高速缓存存储器地址修改器用于高速缓存块提取序列的动态改变
公开(公告)号：US4953079A
公开(公告)日：1990-08-28
申请号：US173406
申请日：1988-03-24
申请人： William P. Ward , Douglas R. Beard
发明人： William P. Ward , Douglas R. Beard
IPC分类号： G06F12/08
CPC分类号： G06F12/0862
摘要： A cache memory includes an address modification circuit for operation during a cache block fetch sequence. The address modification circuit is connected to a polling circuit which receives a first word address from other portions of the cache memory connected to an instruction unit. The polling circuit tests whether a memory module storing the first word is free to make a data return transfer to the cache memory. When the memory module indicates that it is inhibited from making the data return to the cache memory, the address modification circuit selects in order of priority the next word in a cache block to be fetched and polls a memory module storing the next word. Word address selection and polling continues until a free memory module responds or until all words in the cache block have been fetched from main memory.
摘要翻译：高速缓存存储器包括用于在高速缓存块获取序列期间操作的地址修改电路。地址修改电路连接到轮询电路，该轮询电路从连接到指令单元的高速缓冲存储器的其他部分接收第一字地址。轮询电路测试存储第一个字的存储器模块是否可以将数据返回传输到高速缓冲存储器。当存储器模块指示其被禁止使数据返回到高速缓冲存储器时，地址修改电路按优先顺序选择要获取的高速缓存块中的下一个字，并轮询存储下一个字的存储器模块。字地址选择和轮询继续进行，直到可用内存模块响应或直到高速缓存块中的所有单词都已从主内存中取出。

14. 发明授权

US5745721A Partitioned addressing apparatus for vector/scalar registers 失效
标题翻译：用于向量/标量寄存器的分区寻址装置
公开(公告)号：US5745721A
公开(公告)日：1998-04-28
申请号：US485017
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F9/00
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A scalar/vector processor capable of concurrent scaler and vector operations includes scalar resources to process scalar instructions, and vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions. The scalar resources include scalar registers, and the vector resources include vector registers. Decoding means decodes each of a number of address fields. Each field represents a register address to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below a selected moveable address value within a range of addresses encompassed by the address field.
摘要翻译：能够进行并行缩放和向量操作的标量/向量处理器包括用于处理标量指令的标量资源，以及适于与标量资源并行操作并且彼此处理向量指令的向量资源。标量资源包括标量寄存器，矢量资源包括向量寄存器。解码意味着解码多个地址字段中的每一个。每个字段表示寄存器地址，以根据地址字段包含的地址范围内的所选择的可移动地址值高于或低于寄存器地址的值来选择一个标量寄存器或一个向量寄存器。

15. 发明授权

US5640524A Method and apparatus for chaining vector instructions 失效
标题翻译：用于链接向量指令的方法和装置
公开(公告)号：US5640524A
公开(公告)日：1997-06-17
申请号：US395320
申请日：1995-02-28
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F12/00
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A vector processing system includes a main memory, vector registers, vector resources for accessing memory to transfer vector data between main memory and the vector registers and to perform operations on the vector data. Data words stored in non-consecutive address locations of a segment of main memory are accessed for processing. Offset address values of a number of the data words are stored in consecutive elements of a first vector register. A vector gather instruction is executed which adds each offset address value to a base address value to calculate main memory addresses representing main memory storage locations of the data words, retrieves the data words from the main memory, and stores the data words in consecutive elements of a second vector register in an order corresponding to that in which the offset address values are stored in the first vector register. A second vector instruction is chained to the gather instruction for performing an operation upon the retrieved data words and storing the results in a third vector register. A vector scatter instruction is chained to the second vector instruction to return the results to the main memory.
摘要翻译：矢量处理系统包括主存储器，矢量寄存器，用于访问存储器以在主存储器和矢量寄存器之间传送矢量数据的矢量资源，并对矢量数据执行操作。存储在主存储器段的非连续地址位置中的数据字被访问以进行处理。多个数据字的偏移地址值被存储在第一向量寄存器的连续元素中。执行向量收集指令，将每个偏移地址值添加到基地址值以计算表示数据字的主存储器存储位置的主存储器地址，从主存储器检索数据字，并将数据字存储在第二向量寄存器，其顺序与偏移地址值存储在第一向量寄存器中的顺序相对应。第二向量指令被链接到收集指令，用于对检索的数据字执行操作，并将结果存储在第三向量寄存器中。向量散布指令链接到第二个向量指令，以将结果返回到主存储器。

16. 发明授权

US5598547A Vector processor having functional unit paths of differing pipeline lengths 失效
标题翻译：矢量处理器具有不同管线长度的功能单元路径
公开(公告)号：US5598547A
公开(公告)日：1997-01-28
申请号：US478815
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F9/30 , G06F9/32 , G06F9/38 , G06F15/78 , G06F15/80
CPC分类号： G06F9/3873 , G06F15/8076 , G06F15/8092 , G06F9/30021 , G06F9/30094 , G06F9/3013 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3836 , G06F9/3838 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A vector processor includes functional unit paths, each having an input and an output, and with at least one functional unit path including a plurality of pipelined functional elements coupled to the respective path input and output in parallel. The functional elements have different pipeline lengths to complete processing of operands applied to the path input. Program instruction initiation means responds to a first instruction to initiate processing of first operand data in a first of the functional elements, and responds to a second instruction to initiate the processing of second operand data in a second of the functional elements dependent upon completion of the first instruction but only if the second functional element has a pipeline length equal to or greater than the pipeline length of the first functional element.
摘要翻译：矢量处理器包括功能单元路径，每个功能单元路径具有输入和输出，以及至少一个功能单元路径，其包括耦合到相应路径并行输入和输出的多个流水线功能元件。功能元件具有不同的流水线长度，以完成应用于路径输入的操作数的处理。程序指令启动装置响应于第一指令以启动对第一功能元件中的第一操作数数据的处理，并且响应于第二指令以启动第二操作数数据处理功能元件中的第二操作数数据，这取决于完成第一指令，但是仅当第二功能元件具有等于或大于第一功能元件的流水线长度的流水线长度时。

17. 发明授权

US5561784A Interleaved memory access system having variable-sized segments logical address spaces and means for dividing/mapping physical address into higher and lower order addresses 失效
标题翻译：具有可变大小段逻辑地址空间的交错存储器存取系统以及用于将物理地址分割/映射成更高和更低地址的装置
公开(公告)号：US5561784A
公开(公告)日：1996-10-01
申请号：US268660
申请日：1994-06-29
申请人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
发明人： Steve S. Chen , Frederick J. Simmons , George A. Spix , Jimmie R. Wilson , Edward C. Miller , Roger E. Eckert , Douglas R. Beard
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F9/34 , G06F12/10
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A method of accessing common memory in a cluster architecture for a highly parallel multiprocessor scaler/factor computer system using a plurality of segment registers in which is first determined whether a logical address is within a start and end range as defined by the segment registers and then relocating the logical address to a physical address using a displacement value in another segment register.
摘要翻译：一种使用多个段寄存器的高度并行的多处理器缩放器/因子计算机系统的集群架构中访问公共存储器的方法，其中首先确定逻辑地址是否在由段寄存器定义的开始和结束范围内，然后使用另一个段寄存器中的位移值将逻辑地址重定位到物理地址。

18. 发明授权

US5165038A Global registers for a multiprocessor system 失效
标题翻译：多处理器系统的全局寄存器
公开(公告)号：US5165038A
公开(公告)日：1992-11-17
申请号：US536198
申请日：1990-06-11
申请人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
发明人： Douglas R. Beard , George A. Spix , Edward C. Miller , Robert E. Strout, II , Anthony R. Schooler , Alexander A. Silbey , Brian D. Vanderwarn , Jimmie R. Wilson , Richard E. Hessel , Andrew E. Phelps
IPC分类号： G06F15/16 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/167 , G06F15/17 , G06F15/173 , G06F15/78 , G06F15/80
CPC分类号： G06F15/17375 , G06F15/17 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30087 , G06F9/30094 , G06F9/30101 , G06F9/3012 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： Global registers for a multiprocessor system support multiple parallel access paths for simultaneous operations on separate sets of global registers, each set of global registers referred to as a global register file. An arbitration mechanism associated with the global registers is used for resolving multiple, simultaneous requests to a single global register file. An arithmetic and logical unit (ALU) is also associated with each global register file for allowing atomic arithmetic operations to be performed on the entire register value for any of the global registers in that global register file.
摘要翻译：用于多处理器系统的全局寄存器支持多个并行访问路径，用于在单独的全局寄存器集合上同时操作，每组全局寄存器被称为全局寄存器文件。与全局寄存器相关联的仲裁机制用于解析对单个全局寄存器文件的多个同时请求。算术和逻辑单元（ALU）也与每个全局寄存器文件相关联，以允许对该全局寄存器文件中的任何全局寄存器的整个寄存器值执行原子算术运算。

19. 发明授权

US5055707A Method and apparatus for single step clocking on signal paths longer than a clock cycle 失效
标题翻译：在比时钟周期更长的信号路径上进行单步时钟的方法和装置
公开(公告)号：US5055707A
公开(公告)日：1991-10-08
申请号：US568169
申请日：1990-08-16
申请人： Douglas R. Beard
发明人： Douglas R. Beard
IPC分类号： G06F9/38 , G06F11/22 , G06F11/28 , G06F11/30 , G06F11/36
CPC分类号： G06F11/362 , G06F11/22
摘要： An apparatus and method allows for starting and stopping of computer system clocks where the propagation length of signal paths exceed one clock cycle in length. A circular source buffer is provided at the source end of a signal path and saves the data presented on the signal path during every clock cycle. When the system clock has been stopped and is to be restarted, the data stored in the source buffer is copied to a corresponding destination buffer located in the destination end of the signal path. A multiplexer under hardware control located at the destination end of the signal path determines whether the destination receives data from the destination buffer or from the signal path.
摘要翻译：一种装置和方法允许启动和停止信号路径的传播长度超过一个时钟周期的计算机系统时钟。在信号路径的源端提供圆形源缓冲器，并且在每个时钟周期内保存在信号路径上呈现的数据。当系统时钟停止并重新启动时，存储在源缓冲器中的数据被复制到位于信号路径的目的地端的对应目的地缓冲器。位于信号路径的目的地的硬件控制下的复用器确定目的地是否从目的地缓冲器或从信号路径接收数据。

20. 发明授权

US5706490A Method of processing conditional branch instructions in scalar/vector processor 失效
标题翻译：在标量/向量处理器中处理条件分支指令的方法
公开(公告)号：US5706490A
公开(公告)日：1998-01-06
申请号：US484103
申请日：1995-06-07
申请人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
发明人： Douglas R. Beard , Andrew E. Phelps , Michael A. Woodmansee , Richard G. Blewett , Jeffrey A. Lohman , Alexander A. Silbey , George A. Spix , Frederick J. Simmons , Don A. Van Dyke
IPC分类号： G06F12/06 , G06F9/30 , G06F9/32 , G06F9/38 , G06F9/44 , G06F9/45 , G06F11/36 , G06F15/16 , G06F15/173 , G06F15/78 , G06F15/80 , G06F17/16 , G06F9/42
CPC分类号： G06F9/30087 , G06F11/3632 , G06F15/17381 , G06F15/8076 , G06F15/8092 , G06F8/433 , G06F8/45 , G06F9/30021 , G06F9/3004 , G06F9/30094 , G06F9/3013 , G06F9/30138 , G06F9/30141 , G06F9/30149 , G06F9/3802 , G06F9/3804 , G06F9/3814 , G06F9/3816 , G06F9/3828 , G06F9/3834 , G06F9/3836 , G06F9/3838 , G06F9/3846 , G06F9/3855 , G06F9/3857 , G06F9/3875 , G06F9/3885
摘要： A delayed branch mechanism maintains the flow of an instruction pipeline in a scalar/vector processor having an instruction cache and including instruction fetch means, a program counter, and instruction decode/issue means coupled to the instruction cache by means of the instruction pipeline. Conditional branch instructions are rated as likely conditional branch instructions or unlikely conditional branch instructions based on a probability that their branch conditions will be met. A number of pipeline clock periods required for testing the branch conditions are determined. The likely conditional branch instructions are issued and executed including transferring a branch-to-address to the program counter during the number of pipeline clock periods irrespective of a successful meeting of the branch conditions. A number of useful instructions sufficient to issue within the number of pipeline clock periods are placed into the instruction stream following the likely conditional branch instructions. A conditional branch instruction is canceled and returned to an instruction which would have followed the conditional branch instruction if the branch is not taken. No gap occurs in the instruction stream if the corresponding branch is successfully taken.
摘要翻译：延迟分支机制维持具有指令高速缓存的标量/向量处理器中的指令流水线的流程，并且包括通过指令流水线连接到指令高速缓存的指令提取装置，程序计数器和指令解码/发布装置。条件分支指令根据其分支条件将被满足的概率被评为可能的条件分支指令或不可能的条件分支指令。确定测试分支条件所需的多个流水线时钟周期。发出和执行可能的条件分支指令，包括在流水线时钟周期的数量内将分支到地址传送到程序计数器，而不管分支条件的成功满足。在可能的条件分支指令之后，将足以在流水线时钟周期内发出的许多有用指令放入指令流中。条件分支指令被取消并返回到如果不采用分支时将遵循条件分支指令的指令。如果相应的分支成功获取，则在指令流中不会发生间隙。

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