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    • 11. 发明授权
    • Semiconductor memory device for reducing cell area
    • 用于减少电池面积的半导体存储器件
    • US07580313B2
    • 2009-08-25
    • US11589038
    • 2006-10-30
    • Dong-Keun KimJae-Jin Lee
    • Dong-Keun KimJae-Jin Lee
    • G11C8/00
    • G11C7/1069G11C7/1048G11C7/1051G11C7/1078G11C7/1096G11C7/18G11C2207/105
    • A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
    • 一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。 半导体存储器件包括:具有第一和第二单元区域的单元区域; 多个Y解码器,其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线,用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线,用于传送在第二单元区域的位线读出放大器处感测和放大的数据。
    • 16. 发明申请
    • Semiconductor memory device for reducing cell area
    • 用于减少电池面积的半导体存储器件
    • US20050249003A1
    • 2005-11-10
    • US11017683
    • 2004-12-22
    • Dong-Keun KimJae-Jin Lee
    • Dong-Keun KimJae-Jin Lee
    • G11C7/00G11C7/10G11C7/18
    • G11C7/1069G11C7/1048G11C7/1051G11C7/1078G11C7/1096G11C7/18G11C2207/105
    • Disclosed is a semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas, wherein each cell area is provided with a plurality of cell blocks and a plurality of bit line sense amplifying units; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier, wherein the first IO sense amplifier is disposed at one side of the cell area and the second IO sense amplifier is disposed at the other side of the cell area; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
    • 公开了一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。 半导体存储器件包括:具有第一和第二单元区域的单元区域,其中每个单元区域设置有多个单元块和多个位线读出放大单元; 多个Y解码器,其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器,其中第一IO读出放大器设置在单元区域的一侧,第二IO读出放大器设置在单元区域的另一侧; 多个第一数据线,用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线,用于传送在第二单元区域的位线读出放大器处感测和放大的数据。
    • 20. 发明申请
    • NONVOLATILE RANDOM ACCESS MEMORY
    • 非易失性随机存取存储器
    • US20150340087A1
    • 2015-11-26
    • US14811237
    • 2015-07-28
    • Masahiro TAKAHASHIDong Keun KIMHyuck Sang YIM
    • Masahiro TAKAHASHIDong Keun KIMHyuck Sang YIM
    • G11C13/00G11C11/16
    • G11C13/003G11C11/1659G11C11/1673G11C13/0004G11C13/0007G11C13/004G11C2013/0054
    • According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
    • 根据一个实施例,电阻变化存储器包括以下配置。 第一反相器包括第一输入端和第一输出端以及第一和第二电压端。 第二反相器包括第二输入端和第二输出端以及第三和第四电压端。 第二输入端子连接到第一输出端子。 第二输出端子连接到第一输入端子。 第一和第二晶体管分别连接到第一和第二输出端子。 第三和第四晶体管分别连接到第一和第三电压端子。 第五晶体管连接在第一电压端和第一存储单元之间。 第六晶体管连接到第三电压端子。 在关闭第五和第六晶体管之后,控制器接通第一和第二晶体管。