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11. 发明授权

US07580313B2 Semiconductor memory device for reducing cell area 有权
标题翻译：用于减少电池面积的半导体存储器件
公开(公告)号：US07580313B2
公开(公告)日：2009-08-25
申请号：US11589038
申请日：2006-10-30
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C8/00
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： A semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
摘要翻译：一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。半导体存储器件包括：具有第一和第二单元区域的单元区域; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

12. 发明申请

US20090059694A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20090059694A1
公开(公告)日：2009-03-05
申请号：US12005915
申请日：2007-12-28
申请人： Dong-Keun Kim , Seung-Lo Kim
发明人： Dong-Keun Kim , Seung-Lo Kim
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C8/08 , G11C8/06 , G11C8/12
摘要： A semiconductor memory device includes: a reference signal delay unit configured to delay a reference signal for a predetermined operation to output a delayed reference signal; an address delay unit configured to delay a bank address to output a delayed bank address; and a decoding unit configured to receive the delayed reference signal to output a signal for determining a timing of a predetermined operation on a bank selected by the delayed bank address.
摘要翻译：半导体存储器件包括：参考信号延迟单元，被配置为延迟用于预定操作的参考信号以输出延迟的参考信号; 地址延迟单元，被配置为延迟存储体地址以输出延迟的存储体地址; 以及解码单元，被配置为接收延迟的参考信号，以输出用于确定由延迟的存储体地址选择的存储体上的预定操作的定时的信号。

13. 发明授权

US07495983B2 Semiconductor memory device having bit line equalizer in cell array 有权
标题翻译：具有单元阵列中的位线均衡器的半导体存储器件
公开(公告)号：US07495983B2
公开(公告)日：2009-02-24
申请号：US11647370
申请日：2006-12-29
申请人： Dong-Keun Kim
发明人： Dong-Keun Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/12 , G11C7/18
摘要： A semiconductor memory device includes at least one cell array and first and second bit line sense amplifying units. A cell array includes a plurality of bit line pairs and a plurality of bit line equalizers connected to each other through a signal line. Each bit line equalizer equalizes a corresponding bit line pair. The first and the second bit line sense amplifying units are alternately connected to the bit line pairs and receive respective bit line equalization signals.
摘要翻译：半导体存储器件包括至少一个单元阵列和第一和第二位线读出放大单元。单元阵列包括通过信号线彼此连接的多个位线对和多个位线均衡器。每个位线均衡器均衡相应的位线对。第一和第二位线检测放大单元交替地连接到位线对并接收相应的位线均衡信号。

14. 发明申请

US20080081460A1 Method of manufaturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20080081460A1
公开(公告)日：2008-04-03
申请号：US11903610
申请日：2007-09-24
申请人： Chang-Yeon Yoo , Chung-Ki Min , Yung-Jun Kim , Joon-Sang Park , Dong-Keun Kim , Tae-Eun Kim
发明人： Chang-Yeon Yoo , Chung-Ki Min , Yung-Jun Kim , Joon-Sang Park , Dong-Keun Kim , Tae-Eun Kim
IPC分类号： H01L21/4763
CPC分类号： H01L21/76819
摘要： In a method of manufacturing a semiconductor device, a preliminary insulating layer is formed on a substrate. A photoresist pattern is formed on the preliminary insulating layer. A central portion of the preliminary insulating layer is partially etched using the photoresist pattern as an etch mask to form a preliminary insulating layer pattern including a central portion and a peripheral portion on the substrate. The peripheral portion of the photoresist pattern is higher than that of the central portion of the preliminary insulating layer pattern. The preliminary insulating layer pattern is polished to form a planarized insulating layer on the substrate.
摘要翻译：在半导体装置的制造方法中，在基板上形成预备绝缘层。在初级绝缘层上形成光刻胶图形。使用光致抗蚀剂图案作为蚀刻掩模来部分地蚀刻初步绝缘层的中心部分，以在衬底上形成包括中心部分和周边部分的初步绝缘层图案。光致抗蚀剂图案的周边部分比初级绝缘层图案的中心部分高。对初始绝缘层图案进行研磨以在基板上形成平坦化的绝缘层。

15. 发明申请

US20070133989A1 GPON system and method for bandwidth allocation in GPON system 审中-公开
标题翻译： GPON系统中的GPON系统和带宽分配方法
公开(公告)号：US20070133989A1
公开(公告)日：2007-06-14
申请号：US11592274
申请日：2006-11-03
申请人： Yu-Gun Kim , Byeong-Hoon Kim , Tae-Sung Park , Jeong-Won Park , Jai-Young Park , Jong-Kook Kim , Dong-Keun Kim , Su-Hyung Kim , Jae-Young Lee , Jae-Hyun Kim , Hoon-Jae Yeon
发明人： Yu-Gun Kim , Byeong-Hoon Kim , Tae-Sung Park , Jeong-Won Park , Jai-Young Park , Jong-Kook Kim , Dong-Keun Kim , Su-Hyung Kim , Jae-Young Lee , Jae-Hyun Kim , Hoon-Jae Yeon
IPC分类号： H04J14/00
CPC分类号： H04J3/1694 , H04J14/0226 , H04J14/0247 , H04J14/0252 , H04J14/0282
摘要： In a gigabit-capable passive optical network (GPON) system and in a method for bandwidth allocation in a passive optical network (PON) system, a minimum bandwidth is allocated to optical network units (ONUs) for minimal transmission assurance dependent on a traffic characteristic of each ONU, and when there is a traffic-container (T-CONT) class of an ONU not allocated bandwidth after minimum bandwidth allocation to all ONUs, an extra bandwidth remaining after minimum bandwidth allocation is dynamically allocated to each T-CONT class according to a weight of the T-CONT class. Thus, efficient bandwidth allocation, considering fairness between ONUs and priority of each T-CONT, is realized.
摘要翻译：在无源光网络（PON）系统中的千兆位无源光网络（GPON）系统和用于带宽分配的方法中，最小带宽被分配给光网络单元（ONU），以根据流量特性进行最小的传输保证，并且当在所有ONU的最小带宽分配之后没有分配带宽的ONU的业务容器（T-CONT）类别时，在每个T-CONT类别之后动态分配最小带宽分配后剩余的额外带宽，达到T-CONT类的重量。因此，考虑到ONU之间的公平性和每个T-CONT的优先级，实现了有效的带宽分配。

16. 发明申请

US20050249003A1 Semiconductor memory device for reducing cell area 有权
标题翻译：用于减少电池面积的半导体存储器件
公开(公告)号：US20050249003A1
公开(公告)日：2005-11-10
申请号：US11017683
申请日：2004-12-22
申请人： Dong-Keun Kim , Jae-Jin Lee
发明人： Dong-Keun Kim , Jae-Jin Lee
IPC分类号： G11C7/00 , G11C7/10 , G11C7/18
CPC分类号： G11C7/1069 , G11C7/1048 , G11C7/1051 , G11C7/1078 , G11C7/1096 , G11C7/18 , G11C2207/105
摘要： Disclosed is a semiconductor memory device with a reduced cell area and a high-speed data transfer by modifying a circuit layout. The semiconductor memory device includes: a cell area with a first and a second cell areas, wherein each cell area is provided with a plurality of cell blocks and a plurality of bit line sense amplifying units; a plurality of Y decoders of which one Y decoder selects bit line sense amplifiers in the first and the second cell areas; IO sense amplifiers provided with a first IO sense amplifier and a second IO sense amplifier, wherein the first IO sense amplifier is disposed at one side of the cell area and the second IO sense amplifier is disposed at the other side of the cell area; a plurality of first data lines for transferring a data sensed and amplified at the bit line sense amplifier of the first cell area; and a plurality of second data lines for transferring a data sensed and amplified at the bit line sense amplifier of the second cell area.
摘要翻译：公开了一种通过修改电路布局具有减小的单元面积和高速数据传输的半导体存储器件。半导体存储器件包括：具有第一和第二单元区域的单元区域，其中每个单元区域设置有多个单元块和多个位线读出放大单元; 多个Y解码器，其中一个Y解码器在第一和第二单元区域中选择位线读出放大器; 具有第一IO读出放大器和第二IO读出放大器的IO读出放大器，其中第一IO读出放大器设置在单元区域的一侧，第二IO读出放大器设置在单元区域的另一侧; 多个第一数据线，用于传送在第一单元区域的位线读出放大器处感测和放大的数据; 以及多个第二数据线，用于传送在第二单元区域的位线读出放大器处感测和放大的数据。

17. 发明授权

US09336871B2 Resistance change memory 有权
公开(公告)号：US09336871B2
公开(公告)日：2016-05-10
申请号：US14811237
申请日：2015-07-28
申请人： Masahiro Takahashi , Dong Keun Kim , Hyuck Sang Yim
发明人： Masahiro Takahashi , Dong Keun Kim , Hyuck Sang Yim
IPC分类号： G11C7/00 , G11C13/00 , G11C11/16
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.

18. 发明授权

US09298251B2 Methods of spreading plurality of interrupts, interrupt request signal spreader circuits, and systems-on-chips having the same 有权
标题翻译：扩展多个中断的方法，中断请求信号扩展器电路和具有该中断的片上系统
公开(公告)号：US09298251B2
公开(公告)日：2016-03-29
申请号：US13677775
申请日：2012-11-15
申请人： Jae-Gon Lee , Dong-Keun Kim , Si-Young Kim , Jung-Hun Heo
发明人： Jae-Gon Lee , Dong-Keun Kim , Si-Young Kim , Jung-Hun Heo
IPC分类号： G06F1/00 , G06F1/32 , G06F13/24 , G06F9/48 , G06F9/50
CPC分类号： G06F1/3243 , G06F1/3203 , G06F1/3287 , G06F9/4812 , G06F9/5094 , G06F13/24 , Y02D10/152 , Y02D10/22 , Y02D50/20
摘要： In a method of power control for a system-on-chip, output of at least one of a first wakeup request signal and a second wakeup request signal is controlled such that a time interval between the output of the first wakeup request signal and the output of the second wakeup request signal is greater than or equal to a time interval threshold. The first wakeup request signal and the second wakeup request signal are one of concurrent and consecutive wakeup request signals.
摘要翻译：在片上系统的功率控制方法中，控制第一唤醒请求信号和第二唤醒请求信号中的至少一个的输出，使得第一唤醒请求信号的输出与输出之间的时间间隔的第二唤醒请求信号大于或等于时间间隔阈值。第一唤醒请求信号和第二唤醒请求信号是并发和连续的唤醒请求信号之一。

19. 发明授权

US09263114B2 Electronic device 有权
标题翻译：电子设备
公开(公告)号：US09263114B2
公开(公告)日：2016-02-16
申请号：US14563690
申请日：2014-12-08
申请人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
发明人： Ji-Wang Lee , Dong-Keun Kim , Masahiro Takahashi , Tsuneo Inaba
IPC分类号： G11C11/00 , G11C11/16 , G11C13/00 , G11C11/15 , G11C11/56
CPC分类号： G11C11/1673 , G11C11/15 , G11C11/16 , G11C11/1659 , G11C11/5607 , G11C11/5657 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C16/28 , G11C2013/0054 , G11C2213/79
摘要： A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
摘要翻译：半导体存储单元包括根据存储在其中的值具有不同电阻值的第一至第N可变电阻元件，其中N是等于或大于2的自然数; 具有第一参考电阻值的参考电阻元件; 以及分别对应于第一至第N可变电阻元件的第一至第N比较单元，并且每个比较单元确定相应的可变电阻元件的电阻值是否大于或小于第二参考电阻值，其中第一至第N 比较单元通常耦合到参考电阻元件。

20. 发明申请

US20150340087A1 NONVOLATILE RANDOM ACCESS MEMORY 有权
标题翻译：非易失性随机存取存储器
公开(公告)号：US20150340087A1
公开(公告)日：2015-11-26
申请号：US14811237
申请日：2015-07-28
申请人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
发明人： Masahiro TAKAHASHI , Dong Keun KIM , Hyuck Sang YIM
IPC分类号： G11C13/00 , G11C11/16
CPC分类号： G11C13/003 , G11C11/1659 , G11C11/1673 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C2013/0054
摘要： According to one embodiment, a resistance change memory includes the following configuration. A first inverter includes first input and first output terminals and first and second voltage terminals. A second inverter includes second input and second output terminals and third and fourth voltage terminals. The second input terminal is connected to the first output terminal. The second output terminal is connected to the first input terminal. First and second transistors are connected to the first and second output terminals, respectively. Third and fourth transistors are connected to the first and third voltage terminals, respectively. A fifth transistor is connected between the first voltage terminal and the first memory cell. A sixth transistor is connected to the third voltage terminal. A controller turns on the first and second transistors, after turning off the fifth and sixth transistors.
摘要翻译：根据一个实施例，电阻变化存储器包括以下配置。第一反相器包括第一输入端和第一输出端以及第一和第二电压端。第二反相器包括第二输入端和第二输出端以及第三和第四电压端。第二输入端子连接到第一输出端子。第二输出端子连接到第一输入端子。第一和第二晶体管分别连接到第一和第二输出端子。第三和第四晶体管分别连接到第一和第三电压端子。第五晶体管连接在第一电压端和第一存储单元之间。第六晶体管连接到第三电压端子。在关闭第五和第六晶体管之后，控制器接通第一和第二晶体管。

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