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11. 发明授权

US07372323B2 Resonance limiter circuits for an integrated circuit 有权
标题翻译：用于集成电路的共振限幅电路
公开(公告)号：US07372323B2
公开(公告)日：2008-05-13
申请号：US11493104
申请日：2006-07-26
申请人： Vincent R. von Kaenel , Daniel W. Dobberpuhl
发明人： Vincent R. von Kaenel , Daniel W. Dobberpuhl
IPC分类号： H03K5/00
CPC分类号： H03K5/08 , H01L27/0266 , H03K19/00361
摘要： In one embodiment, an integrated circuit comprises resonance limiter circuits coupled to a power supply connection of the integrated circuit. The resonance limiter circuits are configured to detect oscillation on the power supply connection at a resonant frequency, and to dampen the resonant frequency oscillation responsive to detecting the oscillation. In some embodiments, the resonance limiter circuits may damp oscillation at or above the resonant frequency or approximately the resonant frequency (e.g. somewhat below the resonance frequency). The resonant frequency depends on a package of the integrated circuit. In an embodiment, a resonance limiter circuit comprises a filter and a transistor coupled in parallel with the filter between a power supply connection and a ground connection. The filter is tuned to approximately a resonant frequency (e.g. the lowest resonant frequency) that depends on a package corresponding to an integrated circuit into which the resonance limiter circuit is fabricated.
摘要翻译：在一个实施例中，集成电路包括耦合到集成电路的电源连接的谐振限制器电路。谐振限制器电路被配置为以谐振频率检测电源连接上的振荡，并且响应于检测到振荡而衰减谐振频率振荡。在一些实施例中，谐振限制器电路可以抑制或高于谐振频率或近似谐振频率（例如稍微低于谐振频率）的振荡。谐振频率取决于集成电路的封装。在一个实施例中，谐振限制器电路包括滤波器和在电源连接和接地连接之间与滤波器并联耦合的晶体管。将滤波器调谐到大致一个谐振频率（例如，最低谐振频率），该谐振频率取决于与制造谐振限制器电路的集成电路相对应的封装。

12. 发明授权

US06671216B2 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation 有权
公开(公告)号：US06671216B2
公开(公告)日：2003-12-30
申请号：US10349121
申请日：2003-01-22
申请人： Robert Rogenmoser , Steve T. Nishimoto , Daniel W. Dobberpuhl
发明人： Robert Rogenmoser , Steve T. Nishimoto , Daniel W. Dobberpuhl
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C7/12 , G11C17/12
摘要： A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.

13. 发明授权

US06411152B1 Conditional clock buffer circuit 有权
标题翻译：条件时钟缓冲电路
公开(公告)号：US06411152B1
公开(公告)日：2002-06-25
申请号：US09961611
申请日：2001-09-24
申请人： Daniel W. Dobberpuhl
发明人： Daniel W. Dobberpuhl
IPC分类号： G06F104
CPC分类号： H03K19/0016 , G06F1/10
摘要： A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.
摘要翻译：公开了一种条件时钟缓冲电路。在一个实施例中，条件时钟缓冲电路包括经由第一节点和第二节点耦合到预充电电路的预充电电路，第一晶体管和第二晶体管，耦合到第一晶体管和第二晶体管的第三晶体管。可以响应于时钟缓冲器电路外部的状态来激活第一晶体管。当第一晶体管被激活时，可以禁止由时钟缓冲电路驱动的输出时钟信号。

14. 发明授权

US5023480A Push-pull cascode logic 失效
标题翻译：推挽式级联逻辑
公开(公告)号：US5023480A
公开(公告)日：1991-06-11
申请号：US460818
申请日：1990-01-04
申请人： Bruce A. Gieseke , Robert A. Conrad , James J. Montanaro , Daniel W. Dobberpuhl
发明人： Bruce A. Gieseke , Robert A. Conrad , James J. Montanaro , Daniel W. Dobberpuhl
IPC分类号： H03K19/0948 , H03K3/356 , H03K19/173
CPC分类号： H03K3/356147 , H03K19/1738
摘要： A cascode logic circuit provides a pair of differential output nodes that are pulled up by a pair of cross-coupled P-channel output transistors. The output nodes are connected to outputs of an N-channel combinatorial network that receives a differential input and functions to connect one of the output nodes to a positive supply and the other to ground, depending upon the differential input, thus providing a push-pull effect. The output nodes may be connected to the differential output of the combinatorial network by source-drain paths of separate N-channel transistors, with the gates of these transistors connected to the positive supply to capacitively isolate the output nodes from the combinatorial network; alternatively, the gates of these transistors may be clocked. A fully static latch is provided by adding cross-coupled N-channel transistors connecting the output nodes to ground, so the low side of the output is held down instead of being allowed to float. The channel types of the transistors may be reversed in another embodiment; the pull-down transistors of the differential amplifier may be N-channel and the logic and latching transistors P-channel.

15. 发明授权

US07287649B2 System on a chip for packet processing 失效
标题翻译：系统在芯片上进行数据包处理
公开(公告)号：US07287649B2
公开(公告)日：2007-10-30
申请号：US09861188
申请日：2001-05-18
申请人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
发明人： Mark D. Hayter , Shailendra S. Desai , Daniel W. Dobberpuhl , Kwong-Tak A. Chui
IPC分类号： G06F13/00
CPC分类号： H04L47/30 , G06F13/128 , H04L45/00 , H04L45/60 , H04L47/29 , H04L49/103 , H04L49/254 , H04L49/3018 , H04L49/3027 , H04L49/351 , H04L49/90 , H04L49/901 , H04L49/9042
摘要： A packet processing system may include a processor, a cache, a memory controller, and at least one packet interface circuit integrated into a single integrated circuit. In one embodiment (which may be used in integrated or non-integrated systems), the packet interface circuit is configured to cause allocation in the cache of a portion of a received packet. In one embodiment (which may be used in integrated or non-integrated systems), the memory controller may be configured to selectively block memory transactions. Particularly, the memory controller may implement at least two block signals, one for the packet interface circuit and one for other devices. The block signals may be used to control the initiation of memory transactions when the memory controller's input queue is approaching fullness.
摘要翻译：分组处理系统可以包括集成到单个集成电路中的处理器，高速缓存，存储器控制器和至少一个分组接口电路。在一个实施例中（其可以在集成或非集成系统中使用），分组接口电路被配置为在接收到的分组的一部分的高速缓存中引起分配。在一个实施例中（其可以在集成或非集成系统中使用），存储器控制器可以被配置为选择性地阻止存储器事务。特别地，存储器控制器可以实现至少两个块信号，一个用于分组接口电路，一个用于其他设备。当存储器控制器的输入队列逼近时，块信号可用于控制存储器事务的启动。

16. 发明授权

US07276925B2 Operating an integrated circuit at a minimum supply voltage 有权
公开(公告)号：US07276925B2
公开(公告)日：2007-10-02
申请号：US11173684
申请日：2005-07-01
申请人： Daniel W. Dobberpuhl , Vincent R. von Kaenel
发明人： Daniel W. Dobberpuhl , Vincent R. von Kaenel
IPC分类号： G01R31/02
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： In one embodiment, an integrated circuit comprises at least one measurement unit configured to generate an output indicative of a supply voltage at which the integrated circuit is operable for a given operating frequency and a control unit coupled to receive the output. The control unit is configured to generate a voltage control output indicative of a requested supply voltage for the integrated circuit responsive to the output. The voltage control output may be output from the integrated circuit for use by circuitry external to the integrated circuit in generating the supply voltage for the integrated circuit.

17. 发明授权

US06952791B2 Method and circuit for initializing a de-skewing buffer in a clock forwarded system 失效
标题翻译：在时钟转发系统中初始化去偏移缓冲区的方法和电路
公开(公告)号：US06952791B2
公开(公告)日：2005-10-04
申请号：US10044549
申请日：2002-01-11
申请人： James B. Keller , Daniel W. Dobberpuhl
发明人： James B. Keller , Daniel W. Dobberpuhl
IPC分类号： G06F5/10 , H04L7/00 , H04L7/10 , G06F1/04
CPC分类号： G06F5/10 , G06F2205/104 , H04L7/00 , H04L7/0008 , H04L7/005 , H04L7/10
摘要： A method and circuit for initializing a buffer in a clock forwarded system. A buffer is configured for temporarily storing incoming data received on the clock-forwarded interface. The buffer may use a write pointer and a read pointer which may be clocked by two different clocks allowing independent write and read accesses to the buffer. In an initialization mode, a predetermined pattern of data may be written into an entry in the buffer. In one embodiment, a logic circuit may detect the predetermined pattern of data and may cause the value of the write pointer to be captured. A synchronizing circuit may synchronize an indication that the predetermined pattern of data has been detected to the clock used by the read pointer. The synchronizer circuit may then provide a initialize signal to the read pointer which stores the captured write pointer value into the read pointer. This captured write pointer value becomes the initial value of the read pointer, effectively offsetting the read pointer from the write pointer.
摘要翻译：一种用于在时钟转发系统中初始化缓冲器的方法和电路。缓冲区被配置为临时存储在时钟转发接口上接收的输入数据。缓冲器可以使用写指针和读指针，读指针可以由两个不同的时钟计时，从而允许对缓冲器的独立的写和读访问。在初始化模式中，可以将预定的数据模式写入缓冲器中的条目。在一个实施例中，逻辑电路可以检测预定的数据模式，并且可以引起写指针的值被捕获。同步电路可以使已经检测到预定数据模式的指示与读指针使用的时钟同步。同步器电路然后可以向读指针提供初始化信号，该指针将捕获的写指针值存储到读指针中。这个捕获的写指针值成为读指针的初始值，有效地将读指针从写指针中移除。

18. 发明授权

US06657462B2 Conditional clock buffer circuit 有权
公开(公告)号：US06657462B2
公开(公告)日：2003-12-02
申请号：US10349473
申请日：2003-01-22
申请人： Daniel W. Dobberpuhl
发明人： Daniel W. Dobberpuhl
IPC分类号： H03K300
CPC分类号： H03K19/0016 , G06F1/10
摘要： A conditional clock buffer circuit is disclosed. In one embodiment, a conditional clock buffer circuit includes a precharge circuit, a first transistor and a second transistor coupled to the precharge circuit via the first node and the second node, a third transistor coupled to the first transistor and the second transistor. The first transistor may be activated responsive to a condition external to the clock buffer circuit. When the first transistor is activated, an output clock signal driven by the clock buffer circuit may be inhibited.

19. 发明授权

US06538943B2 Method and apparatus to conditionally precharge a partitioned read-only memory with shared wordlines for low power operation 有权
公开(公告)号：US06538943B2
公开(公告)日：2003-03-25
申请号：US10173087
申请日：2002-06-17
申请人： Robert Rogenmoser , Steve T. Nishimoto , Daniel W. Dobberpuhl
发明人： Robert Rogenmoser , Steve T. Nishimoto , Daniel W. Dobberpuhl
IPC分类号： G11C700
CPC分类号： G11C17/18 , G11C7/12 , G11C17/12
摘要： A ROM or other memory may include two or more partitions and a precharge circuit. Each of the partitions may be coupled to separate sets of output conductors, to which the precharge circuit may be coupled. The precharge circuit may precharge the conductors of the partition to be read, while not precharging the other conductors. In one embodiment, the precharge may be to a voltage representing a binary value. In one implementation, the non-precharged conductors may be held to a predetermined voltage different from the voltage to which the precharged conductors are precharged. The predetermined voltage may represent the opposite binary value to the binary value represented by the precharge voltage. The ROM may also include an output circuit which may, in certain embodiments, comprise a logic circuit which logically combines the signals on respective conductors from each partition to provide output signals from the ROM.

20. 发明授权

US5160855A Floating-well CMOS output driver 失效
标题翻译：浮动CMOS输出驱动器
公开(公告)号：US5160855A
公开(公告)日：1992-11-03
申请号：US850248
申请日：1992-03-11
申请人： Daniel W. Dobberpuhl
发明人： Daniel W. Dobberpuhl
IPC分类号： H03K19/003 , H03K19/0185
CPC分类号： H03K19/00315 , H03K19/018521
摘要： A CMOS bi-directional output driver normally operates at 3.3 volts but is capable of communicating with devices that operate at 5 volts.
摘要翻译： CMOS双向输出驱动器通常工作在3.3伏特，但能够与在5伏工作的器件进行通信。

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