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11. 发明申请

US20130246769A1 RUN-TIME INSTRUMENTATION MONITORING FOR PROCESSOR CHARACTERISTIC CHANGES 有权
标题翻译：处理器特性变化的运行时间仪表监控
公开(公告)号：US20130246769A1
公开(公告)日：2013-09-19
申请号：US13422542
申请日：2012-03-16
申请人： Mark S. Farrell , Charles W. Gainey, JR. , Marcel M. Mitran , Damian L. Osisek , Chung-Lung K. Shum , Timothy J. Slegel , Brian L. Smith
发明人： Mark S. Farrell , Charles W. Gainey, JR. , Marcel M. Mitran , Damian L. Osisek , Chung-Lung K. Shum , Timothy J. Slegel , Brian L. Smith
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/45533 , G06F11/3466 , G06F11/348 , G06F11/3644 , G06F2201/86 , G06F2201/88
摘要： Embodiments of the invention relate to monitoring processor characteristic information of a processor using run-time-instrumentation. An aspect of the invention includes executing an instruction stream on the processor and detecting a run-time instrumentation sample point of the executing instruction stream on the processor. A reporting group is stored in a run-time instrumentation program buffer based on the run-time instrumentation sample point. The reporting group includes processor characteristic information associated with the processor.
摘要翻译：本发明的实施例涉及使用运行时间仪器监视处理器的处理器特性信息。本发明的一个方面包括在处理器上执行指令流并检测处理器上的执行指令流的运行时检测采样点。基于运行时仪器采样点，报告组存储在运行时仪表程序缓冲区中。报告组包括与处理器相关联的处理器特性信息。

12. 发明申请

US20130246744A1 MODIFYING RUN-TIME-INSTRUMENTATION CONTROLS FROM A LESSER-PRIVILEGED STATE 有权
公开(公告)号：US20130246744A1
公开(公告)日：2013-09-19
申请号：US13422598
申请日：2012-03-16
申请人： Mark S. Farrell , Charles W. Gainey, JR. , Chung-Lung K. Shum , Timothy J. Slegel
发明人： Mark S. Farrell , Charles W. Gainey, JR. , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F9/312 , G06F9/30
CPC分类号： G06F11/3644 , G06F9/30076 , G06F9/30101 , G06F11/3636 , G06F11/3648
摘要： Embodiments of the invention relate to modifying run-time-instrumentation controls (MRIC) from a lesser-privileged state. The MRIC instruction is fetched. The MRIC instruction includes the address of a run-time-instrumentation control block (RICCB). The RICCB is fetched based on the address included in the MRIC instruction. The RICCB includes values for modifying a subset of the processor's run-time-instrumentation controls. The subset of run-time-instrumentation controls includes a runtime instrumentation program buffer current address (RCA) of a runtime instrumentation program buffer (RIB) location. The RIB holds run-time-instrumentation information of the events recognized by the processor during program execution. The values of the RICCB are loaded into the run-time-instrumentation controls. Event information is provided to the RIB based on the values that were loaded in the run-time-instrumentation control.

13. 发明申请

US20130246741A1 RUN-TIME INSTRUMENTATION DIRECTED SAMPLING 有权
标题翻译：运行时间仪表指示采样
公开(公告)号：US20130246741A1
公开(公告)日：2013-09-19
申请号：US13422532
申请日：2012-03-16
申请人： Charles W. Gainey, JR. , Marcel M. Mitran , Chung-Lung K. Shum , Kevin Stoodley
发明人： Charles W. Gainey, JR. , Marcel M. Mitran , Chung-Lung K. Shum , Kevin Stoodley
IPC分类号： G06F9/312
CPC分类号： G06F11/3466 , G06F9/3005 , G06F11/3636 , G06F11/3644 , G06F11/3648
摘要： Embodiments of the invention relate to implementing run-time instrumentation directed sampling. An aspect of the invention includes fetching a run-time instrumentation next (RINEXT) instruction from an instruction stream. The instruction stream includes the RINEXT instruction followed by a next sequential instruction (NSI) in program order. The method further includes executing the RINEXT instruction by a processor. The executing includes determining whether a current run-time instrumentation state enables setting a sample point for reporting run-time instrumentation information during program execution. Based on the current run-time instrumentation state enabling setting the sample point, the NSI is a sample instruction for causing a run-time instrumentation event. Based on executing the NSI sample instruction, the run-time instrumentation event causes recording of run-time instrumentation information into a run-time instrumentation program buffer as a reporting group.
摘要翻译：本发明的实施例涉及实现运行时仪表定向采样。本发明的一个方面包括从指令流获取运行时仪器下一个（RINEXT）指令。指令流包括RINEXT指令，后面是程序顺序的下一个顺序指令（NSI）。该方法还包括由处理器执行RINEXT指令。该执行包括确定当前运行时仪表状态是否能够在程序执行期间设置用于报告运行时仪表信息的采样点。根据当前的运行时仪器状态设置采样点，NSI是一个用于引起运行时仪表事件的示例指令。基于执行NSI示例指令，运行时仪表事件将运行时仪表信息记录到作为报告组的运行时仪表程序缓冲区中。

14. 发明申请

US20130096901A1 Verifying Simulation Design Modifications 审中-公开
标题翻译：验证仿真设计修改
公开(公告)号：US20130096901A1
公开(公告)日：2013-04-18
申请号：US13271472
申请日：2011-10-12
申请人： Wolfgang Gellerich , Guenter Mayer , Chung-Lung K. Shum , Kai Weber
发明人： Wolfgang Gellerich , Guenter Mayer , Chung-Lung K. Shum , Kai Weber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/504
摘要： A mechanism is provided for verifying design modifications to a simulation design unit included within a simulation model of an integrated electronic device. A modified description is received of a simulation design unit that failed to meet an expected physical property value during an initial simulation of the entire integrated electronic device. A simulation of the simulation design unit is executed using a list of identified input signals from a trace file. The trace file is generated during the initial simulation and indicates state values for the list of identified input signals. A determination is made as to whether the simulation of the simulation design unit fails to meet the expected physical property value. An indication is generated that modifications made to an initial description of the simulation design unit are successful in response to the simulation of the simulation design unit meeting the expected physical property value.
摘要翻译：提供了用于验证对包括在集成电子设备的仿真模型内的模拟设计单元的设计修改的机制。接收到在整个集成电子设备的初始模拟期间不能满足预期物理属性值的模拟设计单元的修改的描述。使用来自跟踪文件的已识别输入信号的列表来执行仿真设计单元的模拟。跟踪文件在初始仿真期间生成，并指示已识别输入信号列表的状态值。确定模拟设计单元的仿真是否不能满足预期的物理属性值。产生对模拟设计单元的初始描述进行的修改成功响应于满足预期物理属性值的模拟设计单元的模拟的指示。

15. 发明授权

US08127118B2 Microarchitecture, method and computer program product for efficient data gathering from a set of trace arrays 失效
标题翻译：微结构，方法和计算机程序产品，用于从一组跟踪数组收集高效数据
公开(公告)号：US08127118B2
公开(公告)日：2012-02-28
申请号：US12036540
申请日：2008-02-25
申请人： Patrick M. West, Jr. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
发明人： Patrick M. West, Jr. , Jane H. Bartik , Martin Recktenwald , Chung-Lung K. Shum , Scott B. Swaney
IPC分类号： G06F9/00 , G06F11/00
CPC分类号： G06F11/3466
摘要： An architecture for collecting performance data in a processor, that includes: a trace read control unit and a trace data collect unit, each unit coupled to a plurality of trace array and multiplex units for providing performance data, the coupling accomplished by a trace read control bus, a data select bus, a trace row address bus and a data return bus; wherein each of the trace array and multiplex units receives a trace read signal and provides data including trace data and the trace read signal to the trace data collect unit. A method and a computer program product are provided.
摘要翻译：一种用于在处理器中收集性能数据的架构，其包括：跟踪读取控制单元和跟踪数据收集单元，每个单元耦合到多个跟踪阵列和用于提供性能数据的多路复用单元，所述耦合由跟踪读取控制总线，数据选择总线，跟踪行地址总线和数据返回总线; 其中每个跟踪阵列和多路复用单元接收跟踪读取信号，并将跟踪数据和跟踪读取信号的数据提供给跟踪数据收集单元。提供了一种方法和计算机程序产品。

16. 发明申请

US20090198964A1 METHOD, SYSTEM, AND COMPUTER PROGRAM PRODUCT FOR OUT OF ORDER INSTRUCTION ADDRESS STRIDE PREFETCH PERFORMANCE VERIFICATION 有权
标题翻译：方法，系统和计算机程序产品，用于订单指令地址纠错性能验证
公开(公告)号：US20090198964A1
公开(公告)日：2009-08-06
申请号：US12023457
申请日：2008-01-31
申请人： Wei-Yi Xiao , Dean G. Bair , Christopher A. Krygowski , Chung-Lung K. Shum
发明人： Wei-Yi Xiao , Dean G. Bair , Christopher A. Krygowski , Chung-Lung K. Shum
IPC分类号： G06F9/312
CPC分类号： G06F9/3851 , G06F11/3457 , G06F12/0862 , G06F2201/885 , G06F2212/6026
摘要： A method, system, and computer program product are provided for verifying out of order instruction address (IA) stride prefetch performance in a processor design having more than one level of cache hierarchies. Multiple instruction streams are generated and the instructions loop back to corresponding instruction addresses. The multiple instruction streams are dispatched to a processor and simulation application to process. When a particular instruction is being dispatched, the particular instruction's instruction address and operand address are recorded in the queue. The processor is monitored to determine if the processor executes fetch and prefetch commands in accordance with the simulation application. It is checked to determine if prefetch commands are issued for instructions having three or more strides.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于在具有多于一个级别的高速缓存层级的处理器设计中验证无序指令地址（IA）跨步预取性能。产生多个指令流，并将指令循环回相应的指令地址。将多个指令流调度到处理器和仿真应用程序进行处理。当调度特定指令时，将特定指令的指令地址和操作数地址记录在队列中。监视处理器以确定处理器是否根据仿真应用执行提取和预取命令。检查是否为具有三个或更多步长的指令发出预取命令。

17. 发明授权

US07082550B2 Method and apparatus for mirroring units within a processor 失效
标题翻译：用于在处理器内镜像单元的方法和装置
公开(公告)号：US07082550B2
公开(公告)日：2006-07-25
申请号：US10435914
申请日：2003-05-12
申请人： Michael Billeci , Chung-Lung K. Shum , Timothy J. Slegel
发明人： Michael Billeci , Chung-Lung K. Shum , Timothy J. Slegel
IPC分类号： G06F11/16
CPC分类号： G06F11/1695 , G06F11/1641
摘要： A processor responsive to a clock cycle includes a base-unit, a mirror-unit that is a duplicate instance of the base-unit, a non-duplicate-unit in signal communication with the base and mirror units, a first staging register disposed at the input to the mirror-unit for delaying the input signal thereto by at least one clock cycle, and a second staging register disposed at the output of the mirror-unit for delaying the output signal therefrom by at least one clock cycle. The non-duplicate-unit includes a comparator for comparing the output signals of the base and mirror units.
摘要翻译：响应于时钟周期的处理器包括基本单元，作为基本单元的重复实例的镜像单元，与基础单元和镜像单元进行信号通信的非重复单元，第一分段寄存器，其布置在用于将输入信号延迟至少一个时钟周期的反射镜单元的输入，以及设置在镜单元的输出处的第二分段寄存器，用于将其输出信号延迟至少一个时钟周期。非重复单元包括用于比较基座和反射镜单元的输出信号的比较器。

18. 发明授权

US07039762B2 Parallel cache interleave accesses with address-sliced directories 失效
标题翻译：并行缓存交错访问与地址片目录
公开(公告)号：US07039762B2
公开(公告)日：2006-05-02
申请号：US10436217
申请日：2003-05-12
申请人： Jennifer A. Navarro , Chung-Lung K. Shum , Aaron Tsai
发明人： Jennifer A. Navarro , Chung-Lung K. Shum , Aaron Tsai
IPC分类号： G06F12/00
CPC分类号： G06F12/1027 , G06F12/0851 , G06F12/1063
摘要： A microprocessor, having interleaved cache and two parallel processing pipelines adapted to access all of the interleaved cache. The microprocessor comprising: a cache directory for each of the parallel processing pipelines wherein each said cache directory is split according to the interleaved cache and interleaving of the cache directory is independent of address bits used for cache interleaving.
摘要翻译：具有交错缓存和适于访问所有交错高速缓存的两个并行处理流水线的微处理器。微处理器包括：用于每个并行处理流水线的高速缓存目录，其中每个所述高速缓存目录根据交错的高速缓冲存储器进行分割，并且高速缓存目录的交织与用于高速缓存交错的地址位无关。

19. 发明授权

US09471315B2 Run-time instrumentation reporting 有权
标题翻译：运行时仪表报告
公开(公告)号：US09471315B2
公开(公告)日：2016-10-18
申请号：US13422552
申请日：2012-03-16
申请人： Mark S. Farrell , Charles W. Gainey, Jr. , Marcel Mitran , Chung-Lung K. Shum , Brian L. Smith
发明人： Mark S. Farrell , Charles W. Gainey, Jr. , Marcel Mitran , Chung-Lung K. Shum , Brian L. Smith
IPC分类号： G06F9/30 , G06F11/36 , G06F9/455
CPC分类号： G06F9/30145 , G06F9/3005 , G06F9/45504 , G06F11/3636 , G06F11/3648
摘要： An aspect includes run-time instrumentation reporting. An instruction stream is executed by a processor. Run-time instrumentation information of the executing instruction stream is captured by the processor. Run-time instrumentation records are created based on the captured run-time instrumentation information. A run-time instrumentation sample point of the executing instruction stream on the processor is detected. A reporting group is stored in a run-time instrumentation program buffer. The storing is based on the detecting and the storing includes: determining a current address of the run-time instrumentation program buffer, the determining based on instruction accessible run-time instrumentation controls; and storing the reporting group into the run-time instrumentation program buffer based on an origin address and the current address of the run-time instrumentation program buffer, the reporting group including the created run-time instrumentation records.
摘要翻译：一方面包括运行时仪器报告。指令流由处理器执行。处理器捕获执行指令流的运行时检测信息。基于捕获的运行时间检测信息创建运行时检测记录。检测处理器上执行指令流的运行时检测采样点。报告组存储在运行时仪表程序缓冲区中。存储是基于检测和存储包括：确定运行时仪表程序缓冲器的当前地址，基于指令可访问的运行时仪表控制的确定; 并且基于源地址和运行时仪表程序缓冲器的当前地址将报告组存储到运行时检测程序缓冲器中，报告组包括创建的运行时仪表记录。

20. 发明授权

US09411599B2 Operand fetching control as a function of branch confidence 有权
标题翻译：操作数获取控制作为分支置信度的函数
公开(公告)号：US09411599B2
公开(公告)日：2016-08-09
申请号：US12822379
申请日：2010-06-24
申请人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
发明人： Christian Jacobi , Barry W. Krumm , Brian R. Prasky , Martin Recktenwald , Chung-Lung K. Shum , Charles F. Webb , Joshua M. Weinberg
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3824 , G06F9/30043 , G06F9/3806 , G06F9/3844 , G06F9/3857
摘要： Data operand fetching control includes a computer processor that includes a control unit for determining memory access operations. The control unit is configured to perform a method. The method includes calculating a summation weight value for each instruction in a pipeline, the summation weight value calculated as a function of branch uncertainty and a pendency in which the instruction resides in the pipeline relative to other instructions in the pipeline. The method also includes mapping the summation weight value of a selected instruction that is attempting to access system memory to a memory access control, each memory access control specifying a manner of handling data fetching operations. The method further includes performing a memory access operation for the selected instruction based upon the mapping.
摘要翻译：数据操作数获取控制包括计算机处理器，其包括用于确定存储器存取操作的控制单元。控制单元被配置为执行方法。该方法包括：计算流水线中每个指令的求和权重值，求和作为分支不确定度的函数计算的求和权重值以及相对于流水线中的其他指令，指令驻留在流水线中的挂起。该方法还包括将尝试访问系统存储器的所选指令的求和权重值映射到存储器访问控制，每个存储器访问控制指定处理数据获取操作的方式。该方法还包括基于映射执行针对所选择的指令的存储器访问操作。

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