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11. 发明申请

US20050221575A1 Novel method to fabricate high reliable metal capacitor within copper back-end process 有权
标题翻译：在铜后端工艺中制造高可靠性金属电容器的新方法
公开(公告)号：US20050221575A1
公开(公告)日：2005-10-06
申请号：US11143229
申请日：2005-06-02
申请人： Chi-Feng Huang , Chun-Hon Chen , Shy-Chy Wong , Chih Lin
发明人： Chi-Feng Huang , Chun-Hon Chen , Shy-Chy Wong , Chih Lin
IPC分类号： H01L21/02 , H01L21/285 , H01L21/314 , H01L21/316 , H01L21/318 , H01L21/768 , H01L21/8242 , H01L21/20
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/3143 , H01L21/31608 , H01L21/31637 , H01L21/3185 , H01L21/76838 , H01L28/75
摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.
摘要翻译：提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。产生金属互连的第一层，在要与其形成电容器的第一互连层的表面上提供交流接触点。使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，以便电容器和设置在下面的衬底中的半导体器件进一步互连。

12. 发明申请

US20050121744A1 High density MIM capacitor structure and fabrication process 有权
标题翻译：高密度MIM电容器结构及制造工艺
公开(公告)号：US20050121744A1
公开(公告)日：2005-06-09
申请号：US10729034
申请日：2003-12-04
申请人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
发明人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
IPC分类号： H01L21/02 , H01L23/522 , H01L27/08 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.
摘要翻译：一种用于形成MIM电容器结构的叠层集成电路（IC）MIM电容器结构及方法，包括形成在包括第一上电极部分和第一下电极部分的第一IMD层中的第一MIM电容器结构; 至少第二MIM电容器结构，以层叠的关系布置在包括第二上电极和第二下电极的上覆IMD层中，以形成MIM电容器堆叠; 其中，所述第一下部电极布置成共同的电信号通信，包括金属填充的通孔与所述第二上部电极和所述第一上部电极被布置成与所述第二下部电极共同的电信号通信。

13. 发明授权

US06329234B1 Copper process compatible CMOS metal-insulator-metal capacitor structure and its process flow 有权
标题翻译：铜工艺兼容CMOS金属 - 绝缘体 - 金属电容器结构及其工艺流程
公开(公告)号：US06329234B1
公开(公告)日：2001-12-11
申请号：US09624026
申请日：2000-07-24
申请人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
发明人： Ssu-Pin Ma , Chun-Hon Chen , Ta-Hsun Yeh , Kuo-Reay Peng , Heng-Ming Hsu , Kong-Beng Thei , Chi-Wu Chou , Yen-Shih Ho
IPC分类号： H01L218238
CPC分类号： H01L28/40 , H01L21/3212 , H01L21/76838 , H01L28/56 , H01L28/60 , H01L28/90
摘要： In many mixed-signal or radio frequency Rf applications, inductors and capacitors are needed at the same time. For a high performance inductor devices, a thick metal layer is needed to increase performance, usually requiring an extra masking process. The present invention describes both a structure and method of fabricating both copper metal-insulator-metal (MIM) capacitors and thick metal inductors, simultaneously, with only one mask, for high frequency mixed-signal or Rf, CMOS applications, in a damascene and dual damascene trench/via process. High performance device structures formed by this invention include: parallel plate capacitor bottom metal (CBM) electrodes and capacitor top metal (CTM) electrodes, metal-insulator-metal (MIM) capacitors, thick inductor metal wiring, interconnects and contact vias.
摘要翻译：在许多混合信号或射频Rf应用中，同时需要电感器和电容器。对于高性能电感器件，需要厚金属层来提高性能，通常需要额外的掩模工艺。本发明同时描述了铜金属 - 绝缘体 - 金属（MIM）电容器和厚金属电感器的结构和方法，同时仅使用一个掩模用于大马士革中的高频混合信号或Rf，CMOS应用，双镶嵌沟/通孔工艺。本发明形成的高性能器件结构包括：平行电容器底部金属（CBM）电极和电容器顶部金属（CTM）电极，金属 - 绝缘体 - 金属（MIM）电容器，厚电感器金属布线，互连和接触通孔。

14. 发明授权

US5880040A Gate dielectric based on oxynitride grown in N.sub.2 O and annealed in NO 失效
标题翻译：基于在N2O中生长并在NO中退火的氮氧化物的栅极电介质
公开(公告)号：US5880040A
公开(公告)日：1999-03-09
申请号：US632178
申请日：1996-04-15
申请人： Shi-Chung Sun , Chun-Hon Chen , Lee-Wei Yen , Chun-Jung Lin
发明人： Shi-Chung Sun , Chun-Hon Chen , Lee-Wei Yen , Chun-Jung Lin
IPC分类号： H01L21/28 , H01L29/51 , H01L21/316
CPC分类号： H01L21/28185 , H01L21/28202 , H01L29/518
摘要： A new technique for the formation of high quality ultrathin gate dielectrics is proposed. Gate oxynitride was first grown in N.sub.2 O and then annealed by in-situ rapid thermal NO-nitridation. This approach has the advantage of providing a tighter nitrogen distribution and a higher nitrogen accumulation at or near the Si--SiO.sub.2 interface than either N.sub.2 O oxynitride or nitridation of SiO.sub.2 in the NO ambient. It is applicable to a wide range of oxide thickness because the initial rapid thermal N.sub.2 O oxidation rate is slow but not as self-limited as NO oxidation. The resulting gate dielectrics have reduced charge trapping, lower stress-induced leakage current and significant resistance to interface state generation under electrical stress.
摘要翻译：提出了一种形成高质量超薄栅极电介质的新技术。氮氧化物首先在N2O中生长，然后通过原位快速热NO氮化退火。这种方法的优点是在NO环境中提供比N2O氮氧化合物或SiO 2的氮化作用更严格的氮分布和在Si-SiO 2界面处或附近的更高的氮积累。它适用于广泛的氧化物厚度，因为初始快速热氧化N2O氧化速率慢但不像NO氧化那样自限制。所得到的栅极电介质具有减少的电荷捕获，较低的应力诱发的漏电流和对电应力下的界面状态产生的显着阻力。

15. 发明申请

US20050206469A1 Interdigitated capacitor and method for fabrication therof 有权
标题翻译：交叉电容器及其制造方法
公开(公告)号：US20050206469A1
公开(公告)日：2005-09-22
申请号：US10804899
申请日：2004-03-19
申请人： Wen-Chin Lin , Denny Tang , Li-Shyue Lai , Chung-Long Chang , Chun-Hon Chen
发明人： Wen-Chin Lin , Denny Tang , Li-Shyue Lai , Chung-Long Chang , Chun-Hon Chen
IPC分类号： H01L23/522 , H01P1/36
CPC分类号： H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A capacitor for use within a microelectronic product employs a first capacitor plate layer that includes a first series of horizontally separated and interconnected tines. A capacitor dielectric layer separates the first capacitor plate layer from a second capacitor plate layer. The second capacitor plate layer includes a second series of horizontally separated and interconnected tines horizontally interdigitated with the first series of horizontally separated and interconnected tines. The capacitor is formed employing a self-aligned method and the capacitor dielectric layer is formed in a serpentine shape.
摘要翻译：在微电子产品中使用的电容器采用第一电容器板层，其包括第一系列水平分离和互连的尖齿。电容器电介质层将第一电容器板层与第二电容器板层分开。第二电容器板层包括与第一系列水平分离和互相联接的齿水平地交叉指向的第二系列水平分离和互连的齿。使用自对准方法形成电容器，并且电容器介电层形成为蛇形形状。

16. 发明申请

US20050077581A1 Metal-over-metal devices and the method for manufacturing same 有权
公开(公告)号：US20050077581A1
公开(公告)日：2005-04-14
申请号：US10683900
申请日：2003-10-10
申请人： Chung-Long Chang , Chun-Hon Chen
发明人： Chung-Long Chang , Chun-Hon Chen
IPC分类号： H01L23/522 , H01L29/76
CPC分类号： H01L23/5222 , H01L2924/0002 , H01L2924/00
摘要： A metal-over-metal (MOM) device and the method for manufacturing same is provided. The device has at least one device cell on a first layer comprising a frame piece and a center piece surrounded by the frame piece. The center piece has a cross-shape center portion defining four quadrants of space between the frame and center pieces. The center piece has one or more center fingers each extending from at least one of the four ends thereof within a quadrant. The frame piece also has one or more frame fingers extending therefrom, each being in at least one quadrant and not being overlapped with the center finger in the same quadrant.

17. 发明授权

US06583491B1 Microelectronic fabrication having microelectronic capacitor structure fabricated therein 有权
标题翻译：在其中制造具有微电子电容器结构的微电子制造
公开(公告)号：US06583491B1
公开(公告)日：2003-06-24
申请号：US10143162
申请日：2002-05-09
申请人： Chi-Feng Huang , Chun-Hon Chen
发明人： Chi-Feng Huang , Chun-Hon Chen
IPC分类号： H01L2900
CPC分类号： H01L28/55
摘要： Within a method for fabricating a microelectronic fabrication, and the microelectronic fabrication fabricated employing the method, there is formed within the microelectronic fabrication a capacitor structure upon a conductor stud layer formed into a first via defined by a patterned dielectric layer to reach a one of a pair of patterned conductor layers within the microelectronic fabrication prior to forming through the patterned dielectric layer a second via to reach the other of the pair of patterned conductor layers within the microelectronic fabrication. The method provides the resulting microelectronic fabrication with enhanced reliability and performance.
摘要翻译：在制造微电子制造的方法和使用该方法制造的微电子制造中，在微电子制造中形成电容器结构，该电容器结构形成在由图案化的介电层限定的第一通孔中的导体柱层上，以达到在微电子制造之前，在通过图案化的电介质层形成第二通孔以达到微电子制造中的一对图案化导体层中的另一个之前，微电子制造中的一对图案化导体层。该方法提供了所得的微电子制造，具有增强的可靠性和性能。

18. 发明授权

US07122878B2 Method to fabricate high reliable metal capacitor within copper back-end process 有权
标题翻译：在铜后端工艺中制造高可靠性金属电容器的方法
公开(公告)号：US07122878B2
公开(公告)日：2006-10-17
申请号：US11143229
申请日：2005-06-02
申请人： Chi-Feng Huang , Chun-Hon Chen , Shy Chy Wong , Chih Hsien Lin
发明人： Chi-Feng Huang , Chun-Hon Chen , Shy Chy Wong , Chih Hsien Lin
IPC分类号： H01L29/00
CPC分类号： H01L28/60 , H01L21/28568 , H01L21/3143 , H01L21/31608 , H01L21/31637 , H01L21/3185 , H01L21/76838 , H01L28/75
摘要： A new method is provided for the creation of a high-reliability metal capacitor as part of back-end processing. A first layer of metal interconnect is created, ac contact point is provided in the surface of the first layer of interconnect aligned with which a capacitor is to be created. A copper interconnect is formed overlying the contact point using TaN for the bottom plate, a high dielectric-constant dielectric material capacitor and using TaN for the top plate. The deposited layers are patterned and etched, a spacer layer is formed over sidewalls of the capacitor to prevent capacitor sidewall leakage. Top interconnect metal is then formed by first depositing a layer of etch stop material for further interconnection of the capacitor and the semiconductor devices provided in the underlying substrate.
摘要翻译：提供了一种用于创建高可靠性金属电容器作为后端处理的一部分的新方法。产生金属互连的第一层，在要与其形成电容器的第一互连层的表面上提供交流接触点。使用用于底板的TaN，高介电常数介电材料电容器和使用TaN作为顶板，形成覆盖接触点的铜互连。沉积的层被图案化和蚀刻，在电容器的侧壁上形成间隔层以防止电容器侧壁泄漏。然后通过首先沉积一层蚀刻停止材料形成顶部互连金属，用于电容器和设置在下面的衬底中的半导体器件的进一步互连。

19. 发明授权

US07050290B2 Integrated capacitor 有权
标题翻译：集成电容
公开(公告)号：US07050290B2
公开(公告)日：2006-05-23
申请号：US10768916
申请日：2004-01-30
申请人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
发明人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
IPC分类号： H01G4/008 , H01G4/20
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.
摘要翻译：实现了具有两个端子的新的电容器装置。该器件包括覆盖衬底的多个第一导电线。每个第一导线连接到电容器装置端子之一。相邻的第一导线连接到相对的端子。第一导线包括多个导电材料。多个第二导线覆盖多个第一导线。每个第二导线连接到电容器件端子中的一个。相邻的第二导线连接到相对的端子。覆盖任何第一导线的任何第二导线连接到相对的端子。第二导线包括多个导电材料。第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。第二介电层位于第一导线和第二导线之间。

20. 发明申请

US20050168914A1 Integrated capacitor 有权
标题翻译：集成电容
公开(公告)号：US20050168914A1
公开(公告)日：2005-08-04
申请号：US10768916
申请日：2004-01-30
申请人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
发明人： Denny Tang , Wen-Chin Lin , Li-Shyue Lai , Chun-Hon Chen , Chung-Long Chang
IPC分类号： H01G4/228 , H01L21/02 , H01L23/522
CPC分类号： H01L28/60 , H01L23/5223 , H01L2924/0002 , H01L2924/00
摘要： A new capacitor device having two terminals is achieved. The device comprises a plurality of first conductive lines overlying a substrate. Each of the first conductive lines is connected to one of the capacitor device terminals. The adjacent first conductive lines are connected to opposite terminals. The first conductive lines comprise a plurality of conductive materials. A plurality of second conductive lines overlie the plurality of first conductive lines. Each of the second conductive lines is connected to one of the capacitive device terminals. Adjacent second conductive lines are connected to opposite terminals. Any second conductive line overlying any first conductive line is connected to an opposite terminal. The second conductive lines comprises a plurality of conductive materials. A first dielectric layer overlies the substrate and lies between the adjacent first conductive lines. A second dielectric layer lies between the first conductive lines and the second conductive lines.
摘要翻译：实现了具有两个端子的新的电容器装置。该器件包括覆盖衬底的多个第一导电线。每个第一导线连接到电容器装置端子之一。相邻的第一导线连接到相对的端子。第一导线包括多个导电材料。多个第二导线覆盖多个第一导线。每个第二导线连接到电容器件端子中的一个。相邻的第二导线连接到相对的端子。覆盖任何第一导线的任何第二导线连接到相对的端子。第二导线包括多个导电材料。第一电介质层覆盖在基板之间并且位于相邻的第一导电线之间。第二介电层位于第一导线和第二导线之间。

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