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11. 发明授权

US06201758B1 Semiconductor memory device permitting time required for writing data to be reduced 失效
标题翻译：允许减少写入数据所需的时间的半导体存储器件
公开(公告)号：US06201758B1
公开(公告)日：2001-03-13
申请号：US09499044
申请日：2000-02-07
申请人： Chikayoshi Morishima , Yasunobu Nakase , Tetsuya Watanabe , Niichi Itoh
发明人： Chikayoshi Morishima , Yasunobu Nakase , Tetsuya Watanabe , Niichi Itoh
IPC分类号： G11C800
CPC分类号： G11C11/419
摘要： A precharge circuit and a bit line load circuit are provided to a read bit line pair. The bit line load circuit continuously supplies a prescribed current to a read bit line. When data is written to one of memory cells selected in common by one read word line, the level of each read bit line will not be lowered to the level of the ground potential by the bit line load circuit if a read word line is activated, and therefore the loads of both discharge and charge operations by transistors in the memory cell are reduced.
摘要翻译：向读位线对提供预充电电路和位线负载电路。位线负载电路将规定的电流连续地提供给读位线。当将数据写入一个读取字线共同选择的存储器单元之一时，如果读取的字线被激活，则每个读取位线的电平将不会被位线负载电路降低到地电位的电平，因此减小存储单元中的晶体管的放电和充电操作的负载。

12. 发明申请

US20080137459A1 Semiconductor memory device allowing high-speed data reading 审中-公开
公开(公告)号：US20080137459A1
公开(公告)日：2008-06-12
申请号：US12010017
申请日：2008-01-18
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C11/413 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1078 , G11C7/1096 , G11C2207/005
摘要： Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.

13. 发明授权

US07161868B2 Multiport semiconductor memory device capable of sufficiently steadily holding data and providing a sufficient write margin 失效
标题翻译：能够充分稳定地保存数据并提供足够的写入裕度的多端口半导体存储器件
公开(公告)号：US07161868B2
公开(公告)日：2007-01-09
申请号：US10880530
申请日：2004-07-01
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C8/00
CPC分类号： G11C11/412 , G11C8/16
摘要： A 2-port SRAM includes a memory cell having: a latch circuit holding potential at storage nodes complementarily; access transistors arranged between the storage nodes and bit lines, respectively, and turned on in response to word lines being activated; a write access transistor and a storage level drive transistor arranged between the storage nodes, respectively, and a ground potential and turned on in response to a first one of the word lines being activated and a sub bit line, respectively, and a write access transistor turned on in response to a second one of the word line being activated and a storage level drive transistor turned on in accordance with a sub bit line.
摘要翻译： 2端口SRAM包括存储单元，存储单元具有：在存储节点互补地保持电位的锁存电路; 布置在存储节点和位线之间的存取晶体管分别响应于字线被激活而导通; 分别布置在存储节点之间的写入存取晶体管和存储电平驱动晶体管和接地电位，并分别响应于第一个字线被激活而导通，并且写入存取晶体管响应于字线中的第二个被激活并且存储电平驱动晶体管根据子位线导通而导通。

14. 发明授权

US06865129B2 Differential amplifier circuit with high amplification factor and semiconductor memory device using the differential amplifier circuit 失效
标题翻译：具有高放大倍数的差分放大电路和使用差分放大电路的半导体存储器件
公开(公告)号：US06865129B2
公开(公告)日：2005-03-08
申请号：US10442978
申请日：2003-05-22
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C11/419 , G11C7/06 , G11C7/10 , G11C11/41 , H03F3/45 , G11C7/00 , G11C7/02 , G11C11/00
CPC分类号： G11C7/1069 , G11C7/065 , G11C7/1072
摘要： A differential amplifier circuit includes a pair of first and second P-type transistors and a pair of first and second enhancement-mode N-type transistors. The first and second P-type transistors have respective gates each connected to the drain of the other P-type transistor, i.e., the first and second P-type transistors are cross-coupled. To respective gates of the first and second N-type transistors, a constant voltage VG (Vth≦VG≦Vdd) is applied. Currents of different magnitudes respectively are applied to first and second input terminals and the first and second N-type transistors generate voltages on first and second output terminals respectively, according to respective currents flowing through the first and second N-type transistors. The differential amplifier circuit is employed as a sense amplifier of a semiconductor memory device for use in reading data.
摘要翻译：差分放大器电路包括一对第一和第二P型晶体管和一对第一和第二增强型N型晶体管。第一和第二P型晶体管具有各自连接到另一个P型晶体管的漏极的栅极，即第一和第二P型晶体管是交叉耦合的。对于第一和第二N型晶体管的各个栅极，施加恒定电压VG（Vth <= VG <= Vdd）。不同幅度的电流分别施加到第一和第二输入端，并且第一和第二N型晶体管分别根据流过第一和第二N型晶体管的各自电流在第一和第二输出端产生电压。差分放大器电路被用作用于读取数据的半导体存储器件的读出放大器。

15. 发明授权

US06297682B1 Differential sense amplifier circuit 失效
标题翻译：差分放大电路
公开(公告)号：US06297682B1
公开(公告)日：2001-10-02
申请号：US09547671
申请日：2000-04-12
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G01R1500
CPC分类号： G11C7/062
摘要： Disclosed is an amplifier circuit comprising: an amplifier 1 which is activated when supplied with a control signal SE and which outputs a pair of amplified signals D and DC; a detection circuit 2 for detecting one of the pair of amplified signals D and DC being changed in potential and outputting a detection signal PO upon detection of the potential change; and a latching circuit 3 which receives a set signal S and the detection signal PO and which outputs the control signal SE. The latching circuit 3 starts outputting the control signal SE in response to an input of the set signal S and terminates the output of the control signal SE upon input of the detection signal PO.
摘要翻译：公开了一种放大器电路，包括：放大器1，其在被提供控制信号SE时被激活，并且输出一对放大信号D和DC; 检测电路2，用于检测一对放大信号D和DC中的一个被改变的电位，并且在检测到电位变化时输出检测信号PO; 以及锁存电路3，其接收设定信号S和检测信号PO，并输出控制信号SE。锁存电路3响应于设定信号S的输入开始输出控制信号SE，并且在输入检测信号PO时终止控制信号SE的输出。

16. 发明授权

US6046611A Semiconductor circuit device with receiver circuit 失效
标题翻译：具有接收电路的半导体电路器件
公开(公告)号：US6046611A
公开(公告)日：2000-04-04
申请号：US89452
申请日：1998-06-03
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： H03K17/04 , H03K5/153 , H03K19/0944
CPC分类号： H03K5/084 , H03K5/1252 , H03K5/2481 , H04L25/0296
摘要： A delay circuit (7) delays a transfer signal (V1) transferred through a transfer signal line (1) by the first delay time (dt1) to generate the first delayed signal (V9) and delays the first delayed signal (V9) by the second delay time (dt2) to generate the second delayed signal (V10). The second current mirror differential amplifier circuit (11) receives the transfer signal (1) and the second delayed signal (V10), whose ground terminal is connected to the first delayed signal line (9). On the other hand, the first current mirror differential amplifier circuit (14) also receives the transfer signal (V1) and the second delayed signal (V10), whose power-supply terminal is connected to the first delayed signal line (9). In response to a rise of the input signal (V1), the circuit (14) starts its operation to change a level of an output signal (V6) from "L" level to "H" level, remaining thereafter. After that, in response to a fall of the input signal (V1), the circuit (11) starts its operation to change the level of the output signal (V6) from "H" level to "L" level. With this configuration, a receiver circuit of a semiconductor circuit device achieves a faster operation and a lower power consumption.
摘要翻译：延迟电路（7）将通过传送信号线（1）传送的传送信号（V1）延迟第一延迟时间（dt1）以产生第一延迟信号（V9），并将第一延迟信号（V9）延迟第二延迟时间（dt2）以产生第二延迟信号（V10）。第二电流镜差分放大器电路（11）接收其接地端子连接到第一延迟信号线（9）的传输信号（1）和第二延迟信号（V10）。另一方面，第一电流镜差分放大器电路（14）还接收其电源端子连接到第一延迟信号线（9）的传输信号（V1）和第二延迟信号（V10）。响应于输入信号（V1）的上升，电路（14）开始其操作，以将输出信号（V6）的电平从“L”电平改变为“H”电平，此后剩余。之后，响应于输入信号（V1）的下降，电路（11）开始其操作，以将输出信号（V6）的电平从“H”电平改变为“L”电平。利用这种配置，半导体电路器件的接收器电路实现更快的操作和更低的功耗。

17. 发明申请

US20080068040A1 SEMICONDUCTOR DEVICE AND IMPEDANCE ADJUSTING METHOD THEREOF 失效
标题翻译：半导体器件及其阻抗调整方法
公开(公告)号：US20080068040A1
公开(公告)日：2008-03-20
申请号：US11852032
申请日：2007-09-07
申请人： Chikayoshi Morishima , Tokuya Osawa , Masaru Haraguchi , Yoshihiro Yamashita
发明人： Chikayoshi Morishima , Tokuya Osawa , Masaru Haraguchi , Yoshihiro Yamashita
IPC分类号： H03K19/0175
CPC分类号： H03K19/0005 , H03K19/018578
摘要： There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.
摘要翻译：提供了一种包括输出缓冲电路的半导体器件，其减少用于阻抗调整的电路占据的面积，并允许高速阻抗调节。在阻抗测量电路中，测量与构成输出缓冲电路的多个晶体管尺寸相同尺寸的参考晶体管的尺寸相等的阻抗值。基于来自阻抗测量电路的测量结果，阻抗代码产生电路将对应于基准晶体管的阻抗值的阻抗代码输出到输出缓冲器代码产生电路。输出缓冲器代码产生电路通过执行算术运算处理产生用于调节输出缓冲器电路的阻抗的输出缓冲器代码，以提供基于阻抗代码的物镜阻抗。

18. 发明授权

US06442087B1 Semiconductor memory device with reduced interference between bit lines 失效
标题翻译：具有减少位线之间干扰的半导体存储器件
公开(公告)号：US06442087B1
公开(公告)日：2002-08-27
申请号：US09968038
申请日：2001-10-02
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G11C700
CPC分类号： H01L27/105 , G11C7/18 , G11C11/419
摘要： Among bit line pairs, the bit line adjacent to the bit line connected to a selected memory cell is maintained in the precharged state, and the bit lines in each pair are disposed sandwiching the bit line of another bit line pair. In a static semiconductor memory device, inter-bit-line interference in the memory cell data reading is reduced, and a changing rate of a bit line voltage amplitude is increased.
摘要翻译：在位线对中，与连接到所选存储单元的位线相邻的位线保持在预充电状态，并且每对中的位线被布置为夹着另一位线对的位线。在静态半导体存储器件中，存储单元数据读取中的位线间干扰减小，并且位线电压幅度的变化率增加。

19. 发明授权

US06337818B1 Semiconductor memory device having a redundancy construction 失效
标题翻译：具有冗余结构的半导体存储器件
公开(公告)号：US06337818B1
公开(公告)日：2002-01-08
申请号：US09773709
申请日：2001-02-02
申请人： Chikayoshi Morishima
发明人： Chikayoshi Morishima
IPC分类号： G01C700
CPC分类号： G11C29/848 , G11C29/808
摘要： A semiconductor memory device includes a plurality of column groups (memory blocks M1 to M9), a plurality of column selection circuits and a plurality of read/write circuits disposed in correspondence with the plurality of column groups, a redundancy selection circuit that selects connection to the read/write circuit by shifting the connection, and input/output circuits that selectively connect an input/output node of the redundancy selection circuit with the data input/output line.
摘要翻译：半导体存储器件包括多个列组（存储器块M1至M9），多个列选择电路和与多个列组相对应设置的多个读/写电路;冗余选择电路，选择与读/写电路，以及选择性地将冗余选择电路的输入/输出节点连接到数据输入/输出线的输入/输出电路。

20. 发明授权

US06327166B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06327166B1
公开(公告)日：2001-12-04
申请号：US09651322
申请日：2000-08-31
申请人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
发明人： Niichi Itoh , Yasunobu Nakase , Tetsuya Watanabe , Chikayoshi Morishima
IPC分类号： G11C502
CPC分类号： H01L27/10844 , H01L27/10897
摘要： Provided is a semiconductor memory having a layout structure in which a memory cell has excellent patterning controllability. A pattern of element components (active regions 10 to 15 and 21 to 23 and polysilicon regions 31 to 42) of a memory cell for one memory cell unit of a memory cell array region 1 is identical to that of a dummy cell of a peripheral dummy cell region 3, and both patterns present a line symmetrical relationship with respect to a boundary line BC1. In addition, a pattern of the memory cell for one memory cell unit of the memory cell array region 1 is identical to that of a dummy cell of a power wiring region 2, and both patterns present a line symmetrical relationship with respect to a boundary line BC2.
摘要翻译：提供一种具有布局结构的半导体存储器，其中存储单元具有优异的图案化可控性。存储单元阵列区域1的一个存储单元单元的存储单元的元件部件（有源区域10至15和21至23以及多晶硅区域31至42）的图案与外围虚拟元件的虚设单元相同单元区域3，并且两个图案相对于边界线BC1呈现线对称关系。此外，存储单元阵列区域1的一个存储单元单元的存储单元的图案与电力布线区域2的虚设单元的图案相同，并且两个图案相对于边界线呈现线对称关系 BC2。

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