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11. 发明申请

WO2007132424A2 MULTI-PROCESSING SYSTEM AND A METHOD OF EXECUTING A PLURALITY OF DATA PROCESSING TASKS 审中-公开
标题翻译：多处理系统和执行数据处理任务的多项式的方法
公开(公告)号：WO2007132424A2
公开(公告)日：2007-11-22
申请号：PCT/IB2007/051824
申请日：2007-05-14
申请人： NXP B.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
CPC分类号： G06F9/48
摘要： A plurality of data processing tasks with processing elements (10) that contend for a resource (18). Execution of each task comprising executing a series of instructions. During execution indications are measured of the speed of progress of executing the instructions for respective ones of the tasks. Requests to access the resource (18) for different ones of the tasks are arbitrated, a priority for judging arbitration being assigned to each task based on the measured indication of the speed of progress of the task. At least over a part of a range of possible speed of progress values increasingly higher priority is assigned in case of increasingly lower indication of the speed of progress.
摘要翻译：具有与资源（18）竞争的处理元件（10）的多个数据处理任务。每个任务的执行包括执行一系列指令。在执行指示期间，测量执行相应任务的指令的进度速度。对不同任务执行资源（18）的请求进行仲裁，根据测量的任务进度指示，判断仲裁分配给每个任务的优先级。至少在可能的进度速度范围内的一部分范围越来越高的优先级被指定为越来越低的进展速度的指示。

12. 发明申请

WO2004084064A3 TYPE CONVERSION UNIT IN A MULTIPROCESSOR SYSTEM 审中-公开
公开(公告)号：WO2004084064A3
公开(公告)日：2004-09-30
申请号：PCT/IB2004/050268
申请日：2004-03-17
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/38
摘要： The invention relates to a very large instruction word (VLIW) processor, comprising a plurality of execution units (101, 103,105), a register file (109, 111, 113) and a communication network (117) for coupling the execution units and the register file. In case of an application specific VLIW processor, i.e. a VLIW processor designed for handling a specific range of applications, the communication network of the VLIW processor may not support all types of data conversions. Therefore, it may turn out that a certain data type conversion is not possible for some applications to be run on such a VLIW processor. By incorporation a type conversion unit (107) in the architecture of the VLIW processor, it can be guaranteed that any desired data type conversion can be performed. In case of a partially connected communication network (117), a communication device (129) can be incorporated as well in the architecture, allowing every execution unit to transfer a value to the type conversion unit, and allowing the type conversion unit to transfer a value to any segment of the distributed register file.

13. 发明申请

WO2004046914A2 VLIW PROCESSOR WITH COPY REGISTER FILE 审中-公开
标题翻译： VLIW处理器与复制寄存器文件
公开(公告)号：WO2004046914A2
公开(公告)日：2004-06-03
申请号：PCT/IB2003/004824
申请日：2003-10-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SRINIVASAN, Balakrishnan , BEKOOIJ, Marco, J., G.
发明人： SRINIVASAN, Balakrishnan , BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/38
CPC分类号： G06F9/3012 , G06F9/30032 , G06F9/30101 , G06F9/30141 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： A compute program is executed in a VLIW processor, which contains a plurality of functional units and a plurality of register files that are each coupled to a respective subset of the functional units. When a first instruction is executed that results in writing of a result to a register file in a register addressed by a result address from the first instruction, the result is copied to a copy register in a register file. The copy register is selected dependent on the register file to which the result was written, but at least partially independent of the result address, so that results written to different addressed registers in the register file are copied to the same register in the copy file. Subsequently a copy instruction may be executed to copy the result from the copy register file to a second register file, from which the result may be used as operand of another instruction.
摘要翻译：在包含多个功能单元和多个寄存器文件的VLIW处理器中执行计算程序，所述功能单元和多个寄存器文件各自耦合到功能单元的相应子集。当第一条指令被执行导致将结果写入寄存器文件中由第一条指令的结果地址寻址的寄存器时，结果将被复制到寄存器文件中的复制寄存器中。复制寄存器的选择取决于写入结果的寄存器文件，但至少部分独立于结果地址，因此写入寄存器文件中不同寻址寄存器的结果将复制到复制文件中的同一寄存器中。随后可执行复制指令以将复制寄存器文件的结果复制到第二寄存器文件，从该文件中可将结果用作另一指令的操作数。

14. 发明申请

WO2003088037A1 VLIW PROCESSOR WITH DATA SPILLING MEANS 审中-公开
标题翻译：具有数据泄漏的VLIW处理器
公开(公告)号：WO2003088037A1
公开(公告)日：2003-10-23
申请号：PCT/IB2003/001364
申请日：2003-04-01
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , DE VRIES, Tromp, J. , BEKOOIJ, Marco, J., G. , AUGUSTEIJN, Alexander , VAN GAGELDONK, Johan, S., H.
发明人： DE VRIES, Tromp, J. , BEKOOIJ, Marco, J., G. , AUGUSTEIJN, Alexander , VAN GAGELDONK, Johan, S., H.
IPC分类号： G06F9/38
CPC分类号： G06F9/3885 , G06F9/30043 , G06F9/3012 , G06F9/3828
摘要： A VLIW processor comprising: a plurality of functional units (1, 3); a distributed register file (4) comprising a plurality of segments (5, 7, 9), the distributed register file (4) being accessible by the functional units (1, 3); a communication unit (11) for communication with a memory; a communication network (13) for coupling the functional units (1, 3) and the distributed register file (4); characterized in that the VLIW processor further comprises a spilling device (15) for transferring data between the distributed register file (4) and the communication unit (11).
摘要翻译：一种VLIW处理器，包括：多个功能单元（1,3）; 分布式寄存器文件（4），包括多个段（5,7,9），所述分配寄存器文件（4）可由所述功能单元（1,3）访问; 用于与存储器通信的通信单元（11）; 用于耦合功能单元（1,3）和分布式寄存器文件（4）的通信网络（13）; 其特征在于，所述VLIW处理器还包括用于在所述分布式寄存器文件（4）和所述通信单元（11）之间传送数据的溢出设备（15）。

15. 发明申请

WO2007132424A8 MULTI-PROCESSING SYSTEM AND A METHOD OF EXECUTING A PLURALITY OF DATA PROCESSING TASKS 审中-公开
标题翻译：多处理系统和执行数据处理任务的多项式的方法
公开(公告)号：WO2007132424A8
公开(公告)日：2008-11-20
申请号：PCT/IB2007051824
申请日：2007-05-14
申请人： NXP BV , BEKOOIJ MARCO J G
发明人： BEKOOIJ MARCO J G
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F9/48
摘要： A plurality of data processing tasks with processing elements (10) that contend for a resource (18). Execution of each task comprising executing a series of instructions. During execution indications are measured of the speed of progress of executing the instructions for respective ones of the tasks. Requests to access the resource (18) for different ones of the tasks are arbitrated, a priority for judging arbitration being assigned to each task based on the measured indication of the speed of progress of the task. At least over a part of a range of possible speed of progress values increasingly higher priority is assigned in case of increasingly lower indication of the speed of progress.
摘要翻译：具有与资源（18）竞争的处理元件（10）的多个数据处理任务。每个任务的执行包括执行一系列指令。在执行指示期间，测量执行相应任务的指令的进度速度。对不同任务执行资源（18）的请求进行仲裁，根据测量的任务进度指示，判断仲裁分配给每个任务的优先级。至少在可能的进度速度范围内的一部分范围越来越高的优先级被指定为越来越低的进展速度的指示。

16. 发明申请

WO2007020577A1 A METHOD AND SYSTEM FOR ACCESSING MEMORY USING AN AUXILIARY MEMORY 审中-公开
标题翻译：使用辅助存储器访问存储器的方法和系统
公开(公告)号：WO2007020577A1
公开(公告)日：2007-02-22
申请号：PCT/IB2006/052777
申请日：2006-08-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/45
CPC分类号： G06F12/0888 , G06F8/4441 , G06F9/3824
摘要： A method and system for accessing memory using an auxiliary memory is presented. According to the invention store and following load instructions accessing same memory locations are identified and a temporal difference is determined. The store instructions comprise an indication for the time interval lapsing until a data element, which is stored by the store instructions, is loaded by a load operation for the first time. Based on this indication the store instruction is given access directly to the main memory or is routed to main memory through an auxiliary memory.
摘要翻译：提出了一种使用辅助存储器访问存储器的方法和系统。根据本发明，存储和跟踪访问相同存储器位置的加载指令被识别并且确定时间差异。存储指令包括时间间隔的指示，直到由存储指令存储的数据元素通过第一次的加载操作加载。基于该指示，存储指令被直接访问主存储器，或通过辅助存储器被路由到主存储器。

17. 发明申请

WO2005036384A3 INSTRUCTION ENCODING FOR VLIW PROCESSORS 审中-公开
标题翻译： VLIW处理器的指令编码
公开(公告)号：WO2005036384A3
公开(公告)日：2005-10-20
申请号：PCT/IB2004052047
申请日：2004-10-11
申请人： KONINKL PHILIPS ELECTRONICS NV , BEKOOIJ MARCO J G , AUGUSTEIJN ALEXANDER , HOOGENDIJK PAUL F
发明人： BEKOOIJ MARCO J G , AUGUSTEIJN ALEXANDER , HOOGENDIJK PAUL F
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30156 , G06F9/3822 , G06F9/3828 , G06F9/3891
摘要： Data processing systems, for example VLIW processors, comprise a register file (RF0, RF1) for storing data, and a number of issue slots (IS0 - IS5), wherein each issue slot has at least one execution unit. The data processing system processes the data stored in the register file, under control of instruction words. Especially in case of a large number of issue slots, it is not always possible to issue an instruction to each issue slot. Therefore the instruction words are often compressed to save instruction memory. A disadvantage is that decoding these compressed instruction words requires complex logic. According to the invention, a first instruction word (IW1) and a second instruction word (IW2) are used. The first instruction word corresponds to a first instruction set, wherein the first instruction word encodes a plurality of instructions to be executed in parallel by the plurality of issue slots. The second instruction word corresponds to a second instruction set, wherein the second instruction word encodes at least one instruction to be executed by a single issue slot. As a result, instructions can be encoded more efficiently. The decoding of the first instruction word becomes faster, since less shifting during decoding is required. The decoding of the second instruction word is achieved with a relatively simple and fast decoder.
摘要翻译：数据处理系统（例如VLIW处理器）包括用于存储数据的寄存器文件（RF0，RF1）和多个发行时隙（IS0-IS5），其中每个发行时隙具有至少一个执行单元。在指令字的控制下，数据处理系统处理存储在寄存器文件中的数据。特别是在大量问题槽的情况下，并不总是可以向每个发布槽发出指令。因此，指令字经常被压缩以保存指令存储器。缺点是解码这些压缩指令字需要复杂的逻辑。根据本发明，使用第一指令字（IW1）和第二指令字（IW2）。第一指令字对应于第一指令集，其中第一指令字对由多个发行时隙并行执行的多个指令进行编码。第二指令字对应于第二指令集，其中第二指令字对由单个发行时隙执行的至少一个指令进行编码。因此，可以更有效地编码指令。第一指令字的解码变得更快，因为需要在解码期间较少的移位。用相对简单且快速的解码器来实现第二指令字的解码。

18. 发明申请

WO2005036384A2 INSTRUCTION ENCODING FOR VLIW PROCESSORS 审中-公开
标题翻译： VLIW处理器的指令编码
公开(公告)号：WO2005036384A2
公开(公告)日：2005-04-21
申请号：PCT/IB2004/052047
申请日：2004-10-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G. , AUGUSTEIJN, Alexander , HOOGENDIJK, Paul, F.
发明人： BEKOOIJ, Marco, J., G. , AUGUSTEIJN, Alexander , HOOGENDIJK, Paul, F.
IPC分类号： G06F9/00
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30156 , G06F9/3822 , G06F9/3828 , G06F9/3891
摘要： Data processing systems, for example VLIW processors, comprise a register file (RF 0 , RF 1 ) for storing data, and a number of issue slots (IS 0 - IS 5 ), wherein each issue slot has at least one execution unit. The data processing system processes the data stored in the register file, under control of instruction words. Especially in case of a large number of issue slots, it is not always possible to issue an instruction to each issue slot. Therefore the instruction words are often compressed to save instruction memory. A disadvantage is that decoding these compressed instruction words requires complex logic. According to the invention, a first instruction word (IW1) and a second instruction word (IW2) are used. The first instruction word corresponds to a first instruction set, wherein the first instruction word encodes a plurality of instructions to be executed in parallel by the plurality of issue slots. The second instruction word corresponds to a second instruction set, wherein the second instruction word encodes at least one instruction to be executed by a single issue slot. As a result, instructions can be encoded more efficiently. The decoding of the first instruction word becomes faster, since less shifting during decoding is required. The decoding of the second instruction word is achieved with a relatively simple and fast decoder.
摘要翻译：数据处理系统，例如VLIW处理器，包括用于存储数据的寄存器文件（RF 0，RF 1）和多个发行时隙（IS _{0 < - sub> 5 ），其中每个发行时隙至少有一个执行单元。数据处理系统在指令字的控制下处理存储在寄存器文件中的数据。特别是在大量发行槽的情况下，并不总是可以向每个发行槽发出指令。因此，指令字通常会被压缩以节省指令内存。缺点是解码这些压缩的指令字需要复杂的逻辑。根据本发明，使用第一指令字（IW1）和第二指令字（IW2）。第一指令字对应于第一指令集，其中第一指令字对由多个发行槽并行执行的多个指令进行编码。第二指令字对应于第二指令集，其中第二指令字对至少一个要由单个发行槽执行的指令进行编码。因此，指令可以更有效地编码。第一个指令字的解码变得更快，因为在解码过程中需要更少的移位。第二个指令字的解码是通过一个相对简单快速的解码器实现的。}

19. 发明申请

WO2004049154A2 A LOOP CONTROL CIRCUIT FOR A DATA PROCESSOR 审中-公开
标题翻译：用于数据处理器的环路控制电路
公开(公告)号：WO2004049154A2
公开(公告)日：2004-06-10
申请号：PCT/IB2003/004962
申请日：2003-10-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUWISSEN, Patrick, P., E. , ENGIN, Nur , VAN BERKEL, Cornelis, H. , BEKOOIJ, Marco, J., G.
发明人： MEUWISSEN, Patrick, P., E. , ENGIN, Nur , VAN BERKEL, Cornelis, H. , BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/325
摘要： A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at least an indication of an end of the loop and a loop count for indicating a number of times the loop should be executed. The loop control circuit (230) detects that one of the loops needs to be executed and in response to said detection, loads the loop information for the corresponding loop, and controls the program counter to execute the corresponding loop according to the loaded loop information. The loop information is initialized in response to a loop initialization instruction (240), where the initialization instruction is issued prior to and independent of a start of the loop initialized by the loop information.
摘要翻译：数据处理器（200）包括用于从由程序计数器（220）指示的指令存储器（210）执行指令的操作执行单元（225）。环路控制电路（230）将多个指令循环的相关联的环路信息存储在寄存器组（232）中。循环信息至少包括循环结束的指示和循环计数，用于指示应该执行循环的次数。环路控制电路（230）检测到需要执行一个环路，并响应于所述检测，加载相应环路的环路信息，并根据加载的环路信息控制程序计数器执行相应的环路。响应于循环初始化指令（240）初始化循环信息，其中初始化指令是在由循环信息初始化的循环的开始之前发出的。

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