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1. 发明申请

WO2007132424A3 MULTI-PROCESSING SYSTEM AND A METHOD OF EXECUTING A PLURALITY OF DATA PROCESSING TASKS 审中-公开
标题翻译：多处理系统和执行多个数据处理任务的方法
公开(公告)号：WO2007132424A3
公开(公告)日：2008-03-27
申请号：PCT/IB2007051824
申请日：2007-05-14
申请人： NXP BV , BEKOOIJ MARCO J G
发明人： BEKOOIJ MARCO J G
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F9/48
摘要： A plurality of data processing tasks with processing elements (10) that contend for a resource (18). Execution of each task comprising executing a series of instructions. During execution indications are measured of the speed of progress of executing the instructions for respective ones of the tasks. Requests to access the resource (18) for different ones of the tasks are arbitrated, a priority for judging arbitration being assigned to each task based on the measured indication of the speed of progress of the task. At least over a part of a range of possible speed of progress values increasingly higher priority is assigned in case of increasingly lower indication of the speed of progress.
摘要翻译：具有争用资源（18）的处理元件（10）的多个数据处理任务。执行每项任务包括执行一系列指令。在执行过程中，测量执行各个任务的指令的进度的速度。针对不同的任务访问资源（18）的请求被仲裁，基于所测量的任务进度速度的指示，判断仲裁的优先级被分配给每个任务。至少在可能的进展速度范围的一部分范围内，越来越低的优先级被分配以指示进度的速度越来越低。

2. 发明申请

WO2007072324A3 MULTI-PROCESSOR CIRCUIT WITH SHARED MEMORY BANKS 审中-公开
标题翻译：具有共享存储器的多处理器电路
公开(公告)号：WO2007072324A3
公开(公告)日：2007-10-18
申请号：PCT/IB2006054807
申请日：2006-12-13
申请人： NXP BV , BEKOOIJ MARCO J G
发明人： BEKOOIJ MARCO J G
IPC分类号： G06F13/16 , G06F13/18
CPC分类号： G06F13/1652 , G06F12/0284
摘要： A plurality of processors (10) in a multiprocessor circuit is coupled to a plurality of independently addressable memory banks (12) via a connection circuit (14). The connection circuit is arranged to forward addresses from a combination of the processors (10) to addressing inputs of memory banks (12) selected by the addresses. The connection circuit (14) provides for a conflict resolution scheme wherein at least one of the processors (10) is associated with an associated one of the memory banks (12) as an associated processor. The connection circuit (14) guarantees the associated processor a higher minimum guaranteed access frequency to said associated one of the memory banks (12) than to a further one of the memory banks (12) other than the associated one of the memory banks (12). A defragmenter (16) detects data associated with a task running on the associated processor (10) that is stored on the further one of the memory banks (12) and move said data to the associated one of the memory banks (12) during execution of the task. The defragmenter cause addressing of the data by the associated processor (10) to be remapped from said further one of the memory banks (12) to the associated one of the banks after said moving, preferably incrementally as movement of data progresses.
摘要翻译：多处理器电路中的多个处理器（10）经由连接电路（14）耦合到多个可独立寻址的存储体（12）。连接电路被布置成将地址从处理器（10）的组合转发到由地址选择的存储体（12）的寻址输入。连接电路（14）提供冲突解决方案，其中处理器（10）中的至少一个与相关联的一个存储体（12）相关联，作为相关处理器。连接电路（14）确保相关联的处理器对存储体（12）中的所述相关联的存储器组（12）之外的存储器（12）中的另一个存储器组（12）之外的相关联的存储器组（12）之间的更高的最小保证访问频率）。碎片整理器（16）检测与存储在存储体（12）中的另一个上的相关处理器（10）上运行的任务相关联的数据，并且在执行期间将所述数据移动到相关联的一个存储体（12）的任务。碎片整理程序使相关联的处理器（10）对数据进行寻址，以在所述移动之后从所述存储体（12）中的另一个重新映射到相应的一个存储体，优选地随着数据的移动而递增地进行。

3. 发明申请

WO2007132424A8 MULTI-PROCESSING SYSTEM AND A METHOD OF EXECUTING A PLURALITY OF DATA PROCESSING TASKS 审中-公开
标题翻译：多处理系统和执行数据处理任务的多项式的方法
公开(公告)号：WO2007132424A8
公开(公告)日：2008-11-20
申请号：PCT/IB2007051824
申请日：2007-05-14
申请人： NXP BV , BEKOOIJ MARCO J G
发明人： BEKOOIJ MARCO J G
IPC分类号： G06F9/48 , G06F9/38
CPC分类号： G06F9/48
摘要： A plurality of data processing tasks with processing elements (10) that contend for a resource (18). Execution of each task comprising executing a series of instructions. During execution indications are measured of the speed of progress of executing the instructions for respective ones of the tasks. Requests to access the resource (18) for different ones of the tasks are arbitrated, a priority for judging arbitration being assigned to each task based on the measured indication of the speed of progress of the task. At least over a part of a range of possible speed of progress values increasingly higher priority is assigned in case of increasingly lower indication of the speed of progress.
摘要翻译：具有与资源（18）竞争的处理元件（10）的多个数据处理任务。每个任务的执行包括执行一系列指令。在执行指示期间，测量执行相应任务的指令的进度速度。对不同任务执行资源（18）的请求进行仲裁，根据测量的任务进度指示，判断仲裁分配给每个任务的优先级。至少在可能的进度速度范围内的一部分范围越来越高的优先级被指定为越来越低的进展速度的指示。

4. 发明申请

WO2004084064A2 TYPE CONVERSION UNIT IN A MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：多处理器系统中的类型转换单元
公开(公告)号：WO2004084064A2
公开(公告)日：2004-09-30
申请号：PCT/IB2004050268
申请日：2004-03-17
申请人： KONINKL PHILIPS ELECTRONICS NV , BEKOOIJ MARCO J G
发明人： BEKOOIJ MARCO J G
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30025 , G06F9/3824
摘要： The invention relates to a very large instruction word (VLIW) processor, comprising a plurality of execution units (101, 103,105), a register file (109, 111, 113) and a communication network (117) for coupling the execution units and the register file. In case of an application specific VLIW processor, i.e. a VLIW processor designed for handling a specific range of applications, the communication network of the VLIW processor may not support all types of data conversions. Therefore, it may turn out that a certain data type conversion is not possible for some applications to be run on such a VLIW processor. By incorporation a type conversion unit (107) in the architecture of the VLIW processor, it can be guaranteed that any desired data type conversion can be performed. In case of a partially connected communication network (117), a communication device (129) can be incorporated as well in the architecture, allowing every execution unit to transfer a value to the type conversion unit, and allowing the type conversion unit to transfer a value to any segment of the distributed register file.
摘要翻译：本发明涉及一种非常大的指令字（VLIW）处理器，它包括多个执行单元（101,103,105），一个寄存器文件（109,111,113）和一个通信网络（117），用于将执行单元和注册文件。在应用专用VLIW处理器（即设计用于处理特定应用范围的VLIW处理器）的情况下，VLIW处理器的通信网络可能不支持所有类型的数据转换。因此，可能会导致某些应用程序在这种VLIW处理器上运行某种数据类型转换是不可能的。通过在VLIW处理器的架构中并入类型转换单元（107），可以保证可以执行任何期望的数据类型转换。在部分连接的通信网络（117）的情况下，也可以在架构中并入通信设备（129），允许每个执行单元将值传送到类型转换单元，并且允许类型转换单元传送分配寄存器文件的任何段的值。

5. 发明申请

WO2006079986A2 DATA PROCESSING SYSTEM AND METHOD FOR MEMORY DEFRAGMENTATION 审中-公开
标题翻译：数据处理系统和存储器扩展方法
公开(公告)号：WO2006079986A2
公开(公告)日：2006-08-03
申请号：PCT/IB2006050279
申请日：2006-01-26
申请人： KONINKL PHILIPS ELECTRONICS NV , BEKOOIJ MARCO J G
发明人： BEKOOIJ MARCO J G
CPC分类号： G06F12/023
摘要： A data processing system is provided in a stream-based communication environment. The data processing system comprises at least one processing unit (PUl, PU2) for a stream-based processing of a plurality of processing jobs (J1-J5), a memory means (MEM) having an address range; and a plurality of FIFOs memory mapped to part of the address range of the memory means (MEM), respectively. Each of the FIFOs is associated to one of said plurality of processing jobs (jl-j5) to enable their communication. An address translation unit (ATU) is provided for identifying address ranges in the memory means (MEM) which are not currently used by the plurality of FIFOs and for moving the address range of at least one FIFO to a currently unused address range in the memory means (MEM).
摘要翻译：在基于流的通信环境中提供数据处理系统。数据处理系统包括用于多个处理作业（J1-J5）的基于流的处理的至少一个处理单元（PU1，PU2），具有地址范围的存储装置（MEM）以及分别映射到存储装置（MEM）的地址范围的一部分的多个FIFO存储器。每个FIFO与所述多个处理作业（jl-j5）中的一个相关联，以使其能够进行通信。提供地址转换单元（ATU），用于识别当前未被多个FIFO使用的存储器装置（MEM）中的地址范围，并且用于将至少一个FIFO的地址范围移动到存储器中的当前未使用的地址范围意思（MEM）。

6. 发明申请

WO2004049154A3 A LOOP CONTROL CIRCUIT FOR A DATA PROCESSOR 审中-公开
标题翻译：用于数据处理器的环路控制电路
公开(公告)号：WO2004049154A3
公开(公告)日：2005-01-20
申请号：PCT/IB0304962
申请日：2003-10-31
申请人： KONINKL PHILIPS ELECTRONICS NV , MEUWISSEN PATRICK P E , ENGIN NUR , VAN BERKEL CORNELIS H , BEKOOIJ MARCO J G
发明人： MEUWISSEN PATRICK P E , ENGIN NUR , VAN BERKEL CORNELIS H , BEKOOIJ MARCO J G
IPC分类号： G06F9/318 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30181 , G06F9/325
摘要： A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at least an indication of an end of the loop and a loop count for indicating a number of times the loop should be executed. The loop control circuit (230) detects that one of the loops needs to be executed and in response to said detection, loads the loop information for the corresponding loop, and controls the program counter to execute the corresponding loop according to the loaded loop information. The loop information is initialized in response to a loop initialization instruction (240), where the initialization instruction is issued prior to and independent of a start of the loop initialized by the loop information.
摘要翻译：数据处理器（200）包括用于从由程序计数器（220）指示的指令存储器（210）执行指令的操作执行单元（225）。环路控制电路（230）将多个指令循环的相关联的环路信息存储在寄存器组（232）中。循环信息至少包括循环结束的指示和循环计数，用于指示应该执行循环的次数。环路控制电路（230）检测到需要执行一个环路，并响应于所述检测，加载相应环路的环路信息，并根据加载的环路信息控制程序计数器执行相应的环路。响应于循环初始化指令（240）初始化循环信息，其中初始化指令是在由循环信息初始化的循环的开始之前发出的。

7. 发明申请

WO2004046914A3 VLIW PROCESSOR WITH COPY REGISTER FILE 审中-公开
标题翻译：具有复制寄存器文件的VLIW处理器
公开(公告)号：WO2004046914A3
公开(公告)日：2004-09-30
申请号：PCT/IB0304824
申请日：2003-10-28
申请人： KONINKL PHILIPS ELECTRONICS NV , SRINIVASAN BALAKRISHNAN , BEKOOIJ MARCO J G
发明人： SRINIVASAN BALAKRISHNAN , BEKOOIJ MARCO J G
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/30032 , G06F9/30101 , G06F9/30141 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： A compute program is executed in a VLIW processor, which contains a plurality of functional units and a plurality of register files that are each coupled to a respective subset of the functional units. When a first instruction is executed that results in writing of a result to a register file in a register addressed by a result address from the first instruction, the result is copied to a copy register in a register file. The copy register is selected dependent on the register file to which the result was written, but at least partially independent of the result address, so that results written to different addressed registers in the register file are copied to the same register in the copy file. Subsequently a copy instruction may be executed to copy the result from the copy register file to a second register file, from which the result may be used as operand of another instruction.
摘要翻译：在VLIW处理器中执行计算程序，VLIW处理器包含多个功能单元和多个寄存器文件，每个寄存器文件各自耦合到功能单元的相应子集。当执行导致将结果写入由第一指令的结果地址寻址的寄存器中的寄存器文件的第一指令时，将结果复制到寄存器文件中的复制寄存器。复制寄存器取决于写入结果的寄存器文件，但至少部分独立于结果地址，因此写入寄存器文件中不同寻址寄存器的结果将复制到复制文件中的同一寄存器。随后，可以执行复制指令以将结果从复制寄存器文件复制到第二寄存器文件，从该寄存器文件可以将结果用作另一个指令的操作数。

8. 发明申请

WO2005036384A3 INSTRUCTION ENCODING FOR VLIW PROCESSORS 审中-公开
标题翻译： VLIW处理器的指令编码
公开(公告)号：WO2005036384A3
公开(公告)日：2005-10-20
申请号：PCT/IB2004052047
申请日：2004-10-11
申请人： KONINKL PHILIPS ELECTRONICS NV , BEKOOIJ MARCO J G , AUGUSTEIJN ALEXANDER , HOOGENDIJK PAUL F
发明人： BEKOOIJ MARCO J G , AUGUSTEIJN ALEXANDER , HOOGENDIJK PAUL F
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30156 , G06F9/3822 , G06F9/3828 , G06F9/3891
摘要： Data processing systems, for example VLIW processors, comprise a register file (RF0, RF1) for storing data, and a number of issue slots (IS0 - IS5), wherein each issue slot has at least one execution unit. The data processing system processes the data stored in the register file, under control of instruction words. Especially in case of a large number of issue slots, it is not always possible to issue an instruction to each issue slot. Therefore the instruction words are often compressed to save instruction memory. A disadvantage is that decoding these compressed instruction words requires complex logic. According to the invention, a first instruction word (IW1) and a second instruction word (IW2) are used. The first instruction word corresponds to a first instruction set, wherein the first instruction word encodes a plurality of instructions to be executed in parallel by the plurality of issue slots. The second instruction word corresponds to a second instruction set, wherein the second instruction word encodes at least one instruction to be executed by a single issue slot. As a result, instructions can be encoded more efficiently. The decoding of the first instruction word becomes faster, since less shifting during decoding is required. The decoding of the second instruction word is achieved with a relatively simple and fast decoder.
摘要翻译：数据处理系统（例如VLIW处理器）包括用于存储数据的寄存器文件（RF0，RF1）和多个发行时隙（IS0-IS5），其中每个发行时隙具有至少一个执行单元。在指令字的控制下，数据处理系统处理存储在寄存器文件中的数据。特别是在大量问题槽的情况下，并不总是可以向每个发布槽发出指令。因此，指令字经常被压缩以保存指令存储器。缺点是解码这些压缩指令字需要复杂的逻辑。根据本发明，使用第一指令字（IW1）和第二指令字（IW2）。第一指令字对应于第一指令集，其中第一指令字对由多个发行时隙并行执行的多个指令进行编码。第二指令字对应于第二指令集，其中第二指令字对由单个发行时隙执行的至少一个指令进行编码。因此，可以更有效地编码指令。第一指令字的解码变得更快，因为需要在解码期间较少的移位。用相对简单且快速的解码器来实现第二指令字的解码。

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