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1. 发明申请

WO2008117246A1 MULTIPROCESSING SYSTEM AND METHOD 审中-公开
标题翻译：多处理系统和方法
公开(公告)号：WO2008117246A1
公开(公告)日：2008-10-02
申请号：PCT/IB2008/051121
申请日：2008-03-26
申请人： NXP B.V. , BEKOOIJ, Marco, J., G. , VAN DEN BRAND, Jan, W.
发明人： BEKOOIJ, Marco, J., G. , VAN DEN BRAND, Jan, W.
IPC分类号： G06F9/46 , G06F9/48
CPC分类号： G06F9/52
摘要： A multiprocessing system executes a plurality of processes concurrently. A process execution circuit (10) issues requests to access a shared resource (16) from the processes. A shared access circuit (14) sequences conflicting ones of the requests. A simulating access circuit (12) generates signals to stall at least one of the processes at simulated stall time points selected as a predetermined function of requests from only the at least one of the processes and/or the timing of the requests from only the at least one of the processes, irrespective of whether said stalling is made necessary by sequencing of conflicting ones of the requests. Thus, part from predetermined maximum response times, predetermined average timing can be guaranteed, independent of the combination of processes that is executed.
摘要翻译：多处理系统同时执行多个处理。处理执行电路（10）从进程发出访问共享资源（16）的请求。共享访问电路（14）对序列中的一个请求进行排序。模拟接入电路（12）产生信号，以使仅在来自所述至少一个的处理和/或来自所述请求的至少一个进程和/或定时的选择作为请求的预定函数选择的模拟停止时间点处的至少一个进程停止至少一个进程，无论是否通过对冲突请求进行排序而使得停止是必要的。因此，可以保证预定的最大响应时间的一部分，与执行的处理的组合无关。

2. 发明申请

WO2007132424A2 MULTI-PROCESSING SYSTEM AND A METHOD OF EXECUTING A PLURALITY OF DATA PROCESSING TASKS 审中-公开
标题翻译：多处理系统和执行数据处理任务的多项式的方法
公开(公告)号：WO2007132424A2
公开(公告)日：2007-11-22
申请号：PCT/IB2007/051824
申请日：2007-05-14
申请人： NXP B.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
CPC分类号： G06F9/48
摘要： A plurality of data processing tasks with processing elements (10) that contend for a resource (18). Execution of each task comprising executing a series of instructions. During execution indications are measured of the speed of progress of executing the instructions for respective ones of the tasks. Requests to access the resource (18) for different ones of the tasks are arbitrated, a priority for judging arbitration being assigned to each task based on the measured indication of the speed of progress of the task. At least over a part of a range of possible speed of progress values increasingly higher priority is assigned in case of increasingly lower indication of the speed of progress.
摘要翻译：具有与资源（18）竞争的处理元件（10）的多个数据处理任务。每个任务的执行包括执行一系列指令。在执行指示期间，测量执行相应任务的指令的进度速度。对不同任务执行资源（18）的请求进行仲裁，根据测量的任务进度指示，判断仲裁分配给每个任务的优先级。至少在可能的进度速度范围内的一部分范围越来越高的优先级被指定为越来越低的进展速度的指示。

3. 发明申请

WO2003083649A1 VLIW PROCESSOR 审中-公开
标题翻译： VLIW处理器
公开(公告)号：WO2003083649A1
公开(公告)日：2003-10-09
申请号：PCT/IB2002/000983
申请日：2002-03-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G. , OLIVEIRA KASTRUP PEREIRA, Bernardo
发明人： BEKOOIJ, Marco, J., G. , OLIVEIRA KASTRUP PEREIRA, Bernardo
IPC分类号： G06F9/38
CPC分类号： G06F9/3891 , G06F9/3012 , G06F9/3824 , G06F9/3826 , G06F9/3828 , G06F9/3885
摘要： A VLIW processor comprising a plurality of functional units (1, 3, 5, 7), a distributed register file (9, 11, 13, 15) accessible by the functional units (1, 3, 5, 7), a partially connected communication network (17) for coupling the functional units (1, 3, 5, 7) and selected parts of the distributed register file (9, 11, 13, 15), characterized in that the VLIW processor further comprises a communication device (29) for coupling the functional units (1, 3, 5, 7) and the distributed register file (9, 11, 13, 15).
摘要翻译：一种VLIW处理器，包括多个功能单元（1,3,5,7），由功能单元（1,3,5,7）可访问的分布式寄存器文件（9,11,13,15），部分连接通信网络（17），用于耦合所述功能单元（1,3,5,7）以及所述分配寄存器文件（9,11,13,15）的选定部分，其特征在于，所述VLIW处理器还包括通信设备（29 ），用于耦合功能单元（1,3,5,7）和分布式寄存器文件（9,11,13,15）。

4. 发明申请

WO2006079986A3 DATA PROCESSING SYSTEM AND METHOD FOR MEMORY DEFRAGMENTATION 审中-公开
公开(公告)号：WO2006079986A3
公开(公告)日：2006-08-03
申请号：PCT/IB2006/050279
申请日：2006-01-26
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
IPC分类号： G06F12/02
摘要： A data processing system is provided in a stream-based communication environment. The data processing system comprises at least one processing unit (PUl, PU2) for a stream-based processing of a plurality of processing jobs (J1-J5), a memory means (MEM) having an address range; and a plurality of FIFOs memory mapped to part of the address range of the memory means (MEM), respectively. Each of the FIFOs is associated to one of said plurality of processing jobs (jl-j5) to enable their communication. An address translation unit (ATU) is provided for identifying address ranges in the memory means (MEM) which are not currently used by the plurality of FIFOs and for moving the address range of at least one FIFO to a currently unused address range in the memory means (MEM).

5. 发明申请

WO2005116830A1 SIGNAL PROCESSING APPARATUS 审中-公开
标题翻译：信号处理装置
公开(公告)号：WO2005116830A1
公开(公告)日：2005-12-08
申请号：PCT/IB2005/051648
申请日：2005-05-20
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/46
CPC分类号： G06F9/4887
摘要： Signal stream processing jobs contain tasks (100), each task (100) to be performed by repeated execution of an operation that processes a chunk of data from a stream. Each job comprises a plurality of the tasks (100) in stream communication with one another. A plurality of processing units (10), which are mutually coupled for the communication of signal streams execute that tasks. A preliminary computation is performed for each job individually, to determine execution parameters required for the job to support a required minimum stream throughput rate if each task of the job is executed in a respective context wherein opportunities to start execution of the task occur separated at most by a cycle time T defined for the task. At run time combination of jobs is selected for execution. Groups of the tasks of the selected combination of jobs are assigned to respective ones of the processing units (10), checking that for each particular processing unit (10) a sum of worst case execution times for the tasks assigned to that particular processing unit (10) does not exceed the defined cycle time T defined for any of the tasks (100) assigned to the particular processing unit (10). The processing unit (10) execute the selected combination of jobs concurrently, each processing unit (10) time multiplexing execution of the group of tasks (100) assigned to that processing unit (10).
摘要翻译：信号流处理作业包含任务（100），每个任务（100）将通过重复执行从流处理数据块的操作来执行。每个作业包括彼此流连接的多个任务（100）。相互耦合用于信号流的通信的多个处理单元（10）执行该任务。为每个作业单独执行初步计算，以确定作业所需的执行参数，以支持所需的最小流吞吐率，如果作业的每个任务在相应的上下文中执行，其中开始执行任务的机会最多分开通过为任务定义的循环时间T。在运行时，选择作业组合执行。将所选择的作业组合的任务组分配给处理单元（10）中的相应处理单元（10），检查对于每个特定处理单元（10），分配给该特定处理单元的任务的最坏情况执行时间的总和（ 10）不超过为分配给特定处理单元（10）的任何任务（100）定义的定义的周期时间T. 处理单元（10）同时执行选择的作业组合，每个处理单元（10）对分配给该处理单元（10）的任务组（100）进行时间复用执行。

6. 发明申请

WO2007020577A1 A METHOD AND SYSTEM FOR ACCESSING MEMORY USING AN AUXILIARY MEMORY 审中-公开
标题翻译：使用辅助存储器访问存储器的方法和系统
公开(公告)号：WO2007020577A1
公开(公告)日：2007-02-22
申请号：PCT/IB2006/052777
申请日：2006-08-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/45
CPC分类号： G06F12/0888 , G06F8/4441 , G06F9/3824
摘要： A method and system for accessing memory using an auxiliary memory is presented. According to the invention store and following load instructions accessing same memory locations are identified and a temporal difference is determined. The store instructions comprise an indication for the time interval lapsing until a data element, which is stored by the store instructions, is loaded by a load operation for the first time. Based on this indication the store instruction is given access directly to the main memory or is routed to main memory through an auxiliary memory.
摘要翻译：提出了一种使用辅助存储器访问存储器的方法和系统。根据本发明，存储和跟踪访问相同存储器位置的加载指令被识别并且确定时间差异。存储指令包括时间间隔的指示，直到由存储指令存储的数据元素通过第一次的加载操作加载。基于该指示，存储指令被直接访问主存储器，或通过辅助存储器被路由到主存储器。

7. 发明申请

WO2005036384A2 INSTRUCTION ENCODING FOR VLIW PROCESSORS 审中-公开
标题翻译： VLIW处理器的指令编码
公开(公告)号：WO2005036384A2
公开(公告)日：2005-04-21
申请号：PCT/IB2004/052047
申请日：2004-10-11
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G. , AUGUSTEIJN, Alexander , HOOGENDIJK, Paul, F.
发明人： BEKOOIJ, Marco, J., G. , AUGUSTEIJN, Alexander , HOOGENDIJK, Paul, F.
IPC分类号： G06F9/00
CPC分类号： G06F9/3885 , G06F9/3012 , G06F9/30156 , G06F9/3822 , G06F9/3828 , G06F9/3891
摘要： Data processing systems, for example VLIW processors, comprise a register file (RF 0 , RF 1 ) for storing data, and a number of issue slots (IS 0 - IS 5 ), wherein each issue slot has at least one execution unit. The data processing system processes the data stored in the register file, under control of instruction words. Especially in case of a large number of issue slots, it is not always possible to issue an instruction to each issue slot. Therefore the instruction words are often compressed to save instruction memory. A disadvantage is that decoding these compressed instruction words requires complex logic. According to the invention, a first instruction word (IW1) and a second instruction word (IW2) are used. The first instruction word corresponds to a first instruction set, wherein the first instruction word encodes a plurality of instructions to be executed in parallel by the plurality of issue slots. The second instruction word corresponds to a second instruction set, wherein the second instruction word encodes at least one instruction to be executed by a single issue slot. As a result, instructions can be encoded more efficiently. The decoding of the first instruction word becomes faster, since less shifting during decoding is required. The decoding of the second instruction word is achieved with a relatively simple and fast decoder.
摘要翻译：数据处理系统，例如VLIW处理器，包括用于存储数据的寄存器文件（RF 0，RF 1）和多个发行时隙（IS _{0 < - sub> 5 ），其中每个发行时隙至少有一个执行单元。数据处理系统在指令字的控制下处理存储在寄存器文件中的数据。特别是在大量发行槽的情况下，并不总是可以向每个发行槽发出指令。因此，指令字通常会被压缩以节省指令内存。缺点是解码这些压缩的指令字需要复杂的逻辑。根据本发明，使用第一指令字（IW1）和第二指令字（IW2）。第一指令字对应于第一指令集，其中第一指令字对由多个发行槽并行执行的多个指令进行编码。第二指令字对应于第二指令集，其中第二指令字对至少一个要由单个发行槽执行的指令进行编码。因此，指令可以更有效地编码。第一个指令字的解码变得更快，因为在解码过程中需要更少的移位。第二个指令字的解码是通过一个相对简单快速的解码器实现的。}

8. 发明申请

WO2004049154A2 A LOOP CONTROL CIRCUIT FOR A DATA PROCESSOR 审中-公开
标题翻译：用于数据处理器的环路控制电路
公开(公告)号：WO2004049154A2
公开(公告)日：2004-06-10
申请号：PCT/IB2003/004962
申请日：2003-10-31
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , MEUWISSEN, Patrick, P., E. , ENGIN, Nur , VAN BERKEL, Cornelis, H. , BEKOOIJ, Marco, J., G.
发明人： MEUWISSEN, Patrick, P., E. , ENGIN, Nur , VAN BERKEL, Cornelis, H. , BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/38
CPC分类号： G06F9/30181 , G06F9/325
摘要： A data processor (200) includes an operation execution unit (225) for executing instructions from an instruction memory (210) indicated by a program counter (220). A loop control circuit (230) stores respective associated loop information for a plurality of instruction loops in a register bank (232). The loop information includes at least an indication of an end of the loop and a loop count for indicating a number of times the loop should be executed. The loop control circuit (230) detects that one of the loops needs to be executed and in response to said detection, loads the loop information for the corresponding loop, and controls the program counter to execute the corresponding loop according to the loaded loop information. The loop information is initialized in response to a loop initialization instruction (240), where the initialization instruction is issued prior to and independent of a start of the loop initialized by the loop information.
摘要翻译：数据处理器（200）包括用于从由程序计数器（220）指示的指令存储器（210）执行指令的操作执行单元（225）。环路控制电路（230）将多个指令循环的相关联的环路信息存储在寄存器组（232）中。循环信息至少包括循环结束的指示和循环计数，用于指示应该执行循环的次数。环路控制电路（230）检测到需要执行一个环路，并响应于所述检测，加载相应环路的环路信息，并根据加载的环路信息控制程序计数器执行相应的环路。响应于循环初始化指令（240）初始化循环信息，其中初始化指令是在由循环信息初始化的循环的开始之前发出的。

9. 发明申请

WO2004084064A3 TYPE CONVERSION UNIT IN A MULTIPROCESSOR SYSTEM 审中-公开
公开(公告)号：WO2004084064A3
公开(公告)日：2004-09-30
申请号：PCT/IB2004/050268
申请日：2004-03-17
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , BEKOOIJ, Marco, J., G.
发明人： BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/38
摘要： The invention relates to a very large instruction word (VLIW) processor, comprising a plurality of execution units (101, 103,105), a register file (109, 111, 113) and a communication network (117) for coupling the execution units and the register file. In case of an application specific VLIW processor, i.e. a VLIW processor designed for handling a specific range of applications, the communication network of the VLIW processor may not support all types of data conversions. Therefore, it may turn out that a certain data type conversion is not possible for some applications to be run on such a VLIW processor. By incorporation a type conversion unit (107) in the architecture of the VLIW processor, it can be guaranteed that any desired data type conversion can be performed. In case of a partially connected communication network (117), a communication device (129) can be incorporated as well in the architecture, allowing every execution unit to transfer a value to the type conversion unit, and allowing the type conversion unit to transfer a value to any segment of the distributed register file.

10. 发明申请

WO2004046914A2 VLIW PROCESSOR WITH COPY REGISTER FILE 审中-公开
标题翻译： VLIW处理器与复制寄存器文件
公开(公告)号：WO2004046914A2
公开(公告)日：2004-06-03
申请号：PCT/IB2003/004824
申请日：2003-10-28
申请人： KONINKLIJKE PHILIPS ELECTRONICS N.V. , SRINIVASAN, Balakrishnan , BEKOOIJ, Marco, J., G.
发明人： SRINIVASAN, Balakrishnan , BEKOOIJ, Marco, J., G.
IPC分类号： G06F9/38
CPC分类号： G06F9/3012 , G06F9/30032 , G06F9/30101 , G06F9/30141 , G06F9/3828 , G06F9/3885 , G06F9/3891
摘要： A compute program is executed in a VLIW processor, which contains a plurality of functional units and a plurality of register files that are each coupled to a respective subset of the functional units. When a first instruction is executed that results in writing of a result to a register file in a register addressed by a result address from the first instruction, the result is copied to a copy register in a register file. The copy register is selected dependent on the register file to which the result was written, but at least partially independent of the result address, so that results written to different addressed registers in the register file are copied to the same register in the copy file. Subsequently a copy instruction may be executed to copy the result from the copy register file to a second register file, from which the result may be used as operand of another instruction.
摘要翻译：在包含多个功能单元和多个寄存器文件的VLIW处理器中执行计算程序，所述功能单元和多个寄存器文件各自耦合到功能单元的相应子集。当第一条指令被执行导致将结果写入寄存器文件中由第一条指令的结果地址寻址的寄存器时，结果将被复制到寄存器文件中的复制寄存器中。复制寄存器的选择取决于写入结果的寄存器文件，但至少部分独立于结果地址，因此写入寄存器文件中不同寻址寄存器的结果将复制到复制文件中的同一寄存器中。随后可执行复制指令以将复制寄存器文件的结果复制到第二寄存器文件，从该文件中可将结果用作另一指令的操作数。

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