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11. 发明授权

US07978493B1 Data encoding scheme to reduce sense current 有权
标题翻译：减少感应电流的数据编码方案
公开(公告)号：US07978493B1
公开(公告)日：2011-07-12
申请号：US12212801
申请日：2008-09-18
申请人： Jun Pin Tan , Tze Swan Tan , Chuan Khye Chai , Boon Jin Ang , Kar Keng Chua
发明人： Jun Pin Tan , Tze Swan Tan , Chuan Khye Chai , Boon Jin Ang , Kar Keng Chua
IPC分类号： G11C17/00
CPC分类号： G11C17/18 , G11C17/16
摘要： Techniques for encoding and decoding fuse data to reduce sense current are disclosed. An embodiment to encode fuse sense data includes inverting each of the bits of the fuse data and using an individual fuse as a flag bit to record the data inversion. The states of the respective fuses may represent different logic states. A fuse may be blown to indicate a logic one and likewise, an unblown fuse may indicate a logic zero. A blown fuse and an unblown fuse may have different current consumption. An unblown fuse may consume more sensing current compared to a blown fuse. Another embodiment to decode the encoded fuse data includes embedded logic circuits and a separate fuse as a flag bit. Encoding and decoding fuse data may reduce fuse sensing current.
摘要翻译：公开了用于编码和解码熔丝数据以减少感测电流的技术。编码熔丝检测数据的实施例包括将熔丝数据的每一位反转并使用单独的熔丝作为标记位来记录数据反转。各个保险丝的状态可以表示不同的逻辑状态。熔断器可能会被烧断以指示逻辑电路，同样，未熔断的保险丝可能指示逻辑零。熔断的保险丝和未熔断的保险丝可能具有不同的电流消耗。与熔断保险丝相比，未熔断的保险丝可能消耗更多的感测电流。解码编码熔丝数据的另一个实施例包括嵌入式逻辑电路和单独的保险丝作为标志位。熔丝数据的编码和解码可以减少熔丝感应电流。

12. 发明授权

US07975082B2 System and method to facilitate deterministic testing of data transfers between independent clock domains on a chip 有权
标题翻译：系统和方法，以促进芯片上独立时钟域之间的数据传输的确定性测试
公开(公告)号：US07975082B2
公开(公告)日：2011-07-05
申请号：US12478696
申请日：2009-06-04
申请人： Frank C. Chiu , Ian Jones , Anup Pradhan , Iain Robertson
发明人： Frank C. Chiu , Ian Jones , Anup Pradhan , Iain Robertson
IPC分类号： G06F3/00 , G06F5/00
CPC分类号： G06F13/4278
摘要： A system and method of deterministically transferring data across a first clock domain to a second clock domain includes receiving a resynchronize command, initiating a corresponding one of a plurality of read delays in each one of a second plurality of devices in the second clock domain, counting down the plurality of read delays to zero, receiving a training pattern after the plurality of read delays count down to zero in each one of the second plurality of devices, recovering a clock data in each of the second plurality of devices, receiving a synch byte by each of the second plurality of devices, selecting one of a plurality of serial lanes as a reference lane, wherein the plurality of serial lanes couple the first clock domain to the second clock domain, initiating a write pointer, writing n bytes of serial data to a buffer and converting the n bytes of data from serial data to parallel data in a serial to parallel converter such that the serial n byte data in the buffer are aligned in time.
摘要翻译：确定性地将数据传送到第一时钟域到第二时钟域的系统和方法包括接收重新同步命令，启动第二时钟域中的第二多个设备中的每一个中的多个读延迟中的相应一个读数延迟，计数将所述多个读延迟降低为零，在所述第二多个设备中的每一个中的所述多个读延迟中的所述多个读延迟之后接收到训练模式，从而恢复每个所述第二多个设备中的时钟数据，接收同步字节通过所述第二多个设备中的每一个，选择多个串行通道中的一个作为参考通道，其中所述多个串行通道将所述第一时钟域耦合到所述第二时钟域，启动写指针，写入n字节的串行数据到缓冲器并将串行数据中的n字节数据转换成并行转换器中的并行数据，使得缓冲器中的串行n字节数据对齐及时。

13. 发明授权

US07957031B2 High-image-quality halftone process 失效
公开(公告)号：US07957031B2
公开(公告)日：2011-06-07
申请号：US11601509
申请日：2006-11-17
申请人： Toshiaki Kakutani
发明人： Toshiaki Kakutani
IPC分类号： H04N1/405 , H04N1/407
CPC分类号： H04N1/40087
摘要： An image processing method involves processing image data indicative of an image represented with a prescribed number of input tones by each of pixel groups composed of a plurality of print pixels, and generating dot data representing a status of dot formation on each of the print pixels to be formed on a print medium. The method includes preparing a first conversion table and a second conversion table, determining the pixel group tone value in response to the input tone value corresponding to the pixel group, converting the determined pixel group tone value into the code values for each of the pixel groups, by referring to the first conversion table, decoding the acquired code value into the output dot arrangement for each of the pixel groups, by referring to the second conversion table, and outputting the dot data in response to the output dot arrangement.

14. 发明授权

US07953297B2 Generation of high-resolution images based on multiple low-resolution images 失效
标题翻译：基于多个低分辨率图像生成高分辨率图像
公开(公告)号：US07953297B2
公开(公告)日：2011-05-31
申请号：US12658684
申请日：2010-02-12
申请人： Seiji Aiso
发明人： Seiji Aiso
IPC分类号： G06K9/32
CPC分类号： G06T3/4069
摘要： The procedure of the present invention estimates a correction rate for elimination of a positional shift between the multiple first images, executes correction with the estimated correction rate to eliminate the positional shift between the multiple first images, and combines the multiple corrected first images to generate the second image. The procedure selects a target pixel among pixels included in the second image, and detects multiple adjacent pixels respectively in the multiple first images, which adjoin to the selected target pixel. The procedure then selects an image as a composition object or a composition object image with regard to the target pixel among the multiple first images according to the multiple adjacent pixels, and calculates a pixel value of the target pixel based on the composition object image. The procedure excludes the first image that includes a certain adjacent pixel out of the multiple adjacent pixels, which is detected to have a motion relative to one base image selected among the multiple first images, from the composition object image with regard to the target pixel. This arrangement of the invention enables generation of a high-resolution still image by taking into account motions of image parts.
摘要翻译：本发明的方法估计用于消除多个第一图像之间的位置偏移的校正速率，以估计的校正速率执行校正以消除多个第一图像之间的位置偏移，并且组合多个经校正的第一图像以产生第二张图片。该过程选择包括在第二图像中的像素中的目标像素，并且在与所选择的目标像素相邻的多个第一图像中分别检测多个相邻像素。然后，该过程根据多个相邻像素在多个第一图像之中针对目标像素选择图像作为合成对象或合成对象图像，并且基于合成对象图像来计算目标像素的像素值。该程序从关于目标像素的合成对象图像中排除包括多个相邻像素中的某个相邻像素的第一图像，其被检测为具有相对于在多个第一图像中选择的一个基本图像的运动。通过考虑图像部分的运动，本发明的这种布置能够产生高分辨率静止图像。

15. 发明授权

US07949780B2 Adaptive flow control techniques for queuing systems with multiple producers 有权
标题翻译：具有多个生产者的排队系统的自适应流量控制技术
公开(公告)号：US07949780B2
公开(公告)日：2011-05-24
申请号：US12022056
申请日：2008-01-29
申请人： Charles E. Suresh
发明人： Charles E. Suresh
IPC分类号： G06F15/16 , H04L12/26 , H04L12/28
CPC分类号： G06F9/505
摘要： Provided is a method, computer program and system for controlling the flow of service requests originated by a plurality of requesters. The method includes adding an additional control mechanism, which includes a serializer and a serializer queue, between the requesters and the service provider. The serializer inhibits the requesters when the serializer queue size reaches a threshold for a period proportional to the number of requesters already waiting, the queue length and the serializer service time. When the service provider queue is full or at a critical level, the serializer is inhibited for a period of time that is the approximately the difference between the service times of the serializer and the service provider. In addition, when the service provider queue is full, the service provider service time is recalculated as a function of the serializer service time and of the time required to process requests by the service provider.
摘要翻译：提供了一种用于控制由多个请求者发起的服务请求的流程的方法，计算机程序和系统。该方法包括在请求者和服务提供商之间添加一个附加控制机制，其中包括一个串行器和一个串行化器队列。当串行器队列大小达到一个与已经等待的请求者数量，队列长度和序列化器服务时间成正比的时间段时，串行器禁止请求者。当服务提供商队列已满或处于关键级别时，串行器被禁止一段时间，这是串行器和服务提供商的服务时间之间的大致差异。另外，当服务提供者队列已满时，服务提供商服务时间被重新计算为串行器服务时间以及服务提供商处理请求所需的时间的函数。

16. 发明授权

US07946303B2 Carrier for reducing entrance and/or exit marks left by a substrate-processing meniscus 失效
标题翻译：用于减少基板处理弯月面留下的入口和/或出口痕迹的载体
公开(公告)号：US07946303B2
公开(公告)日：2011-05-24
申请号：US11537501
申请日：2006-09-29
申请人： Robert O'Donnell , Eric Lenz , Mark Wilcoxson , Mike Ravkin , Alexander A. Yatskar
发明人： Robert O'Donnell , Eric Lenz , Mark Wilcoxson , Mike Ravkin , Alexander A. Yatskar
IPC分类号： B08B3/04 , B23Q1/25
CPC分类号： H01L21/67051 , H01L21/6708 , Y10S134/902 , Y10S269/90 , Y10S269/902 , Y10T29/49826
摘要： A carrier for supporting a substrate during processing by a meniscus formed by upper and lower proximity heads is described. The carrier includes a frame having an opening sized for receiving a substrate and a plurality of support pins for supporting the substrate within the opening. The opening is slightly larger than the substrate such that a gap exists between the substrate and the opening. Means for reducing a size and frequency of entrance and/or exit marks on substrates is provided, the means aiding and encouraging liquid from the meniscus to evacuate the gap. A method for reducing the size and frequency of entrance and exit marks is also provided.
摘要翻译：描述了在由上下接近头形成的弯液面的处理期间支撑衬底的载体。载体包括具有开口的框架，该开口的尺寸用于容纳基底和用于将基底支撑在开口内的多个支撑销。开口略大于基板，使得基板和开口之间存在间隙。提供了用于减小基板上的入口和/或出口痕迹的尺寸和频率的手段，该装置帮助和鼓励来自弯月面的液体以排出间隙。还提供了用于减小入口和出口标记的尺寸和频率的方法。

17. 发明授权

US07945085B2 User interface for wafer data analysis and visualization 失效
标题翻译：用于晶圆数据分析和可视化的用户界面
公开(公告)号：US07945085B2
公开(公告)日：2011-05-17
申请号：US12772881
申请日：2010-05-03
申请人： Jorge Luque
发明人： Jorge Luque
IPC分类号： G06K9/00
CPC分类号： H01L22/20
摘要： A wafer viewer system is provided for graphical presentation and analysis of a wafer and a wafer series. More specifically, the wafer viewer system includes a graphical user interface for displaying a wafer, graphically selecting regions of the wafer for analysis, performing analysis on the selected regions of the wafer, and displaying results of the analysis.
摘要翻译：提供晶片观察器系统用于晶片和晶片系列的图形显示和分析。更具体地，晶片观察器系统包括用于显示晶片的图形用户界面，图形地选择用于分析的晶片的区域，对晶片的选定区域进行分析，并显示分析结果。

18. 发明授权

US07940082B1 Circuits and method for bypassing a static configuration in a programmable logic device to implement a dynamic multiplexer 有权
标题翻译：绕过可编程逻辑器件中的静态配置以实现动态多路复用器的电路和方法
公开(公告)号：US07940082B1
公开(公告)日：2011-05-10
申请号：US12053183
申请日：2008-03-21
申请人： Adam J. Wright
发明人： Adam J. Wright
IPC分类号： H03K19/177
CPC分类号： H03K19/1737
摘要： Circuit for selectively using static or dynamic select signals inside an integrated circuit, including a first transistor connecting a static select signal to a dynamic route select output line when a dynamic select CRAM signal is at a first logical level, and a second transistor connecting a dynamic select signal to the dynamic route select output line when the dynamic select CRAM signal is at a second logical level. The circuit further comprises a dynamic select CRAM register that contains a logical value to indicate whether the dynamic select signal bypasses the static select signal. The dynamic select CRAM register is connected to the second transistor gate, and to an inverter whose output is connected to the first transistor gate.
摘要翻译：用于选择性地使用集成电路内的静态或动态选择信号的电路，包括当动态选择CRAM信号处于第一逻辑电平时将静态选择信号连接到动态路径选择输出线的第一晶体管，以及连接动态当动态选择CRAM信号处于第二逻辑电平时，选择信号到动态路由选择输出线路。电路还包括动态选择CRAM寄存器，其包含用于指示动态选择信号是否绕过静态选择信号的逻辑值。动态选择CRAM寄存器连接到第二晶体管栅极，并连接到其输出连接到第一晶体管栅极的反相器。

19. 发明授权

US07925822B2 Erase count recovery 有权
标题翻译：擦除计数恢复
公开(公告)号：US07925822B2
公开(公告)日：2011-04-12
申请号：US12023090
申请日：2008-01-31
申请人： Amir Mosek
发明人： Amir Mosek
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0246 , G06F2212/7211
摘要： An erase count of a flash memory block which is lost, e.g., due to power failure is updated or replaced by using known erase counts of other blocks of the flash memory. A flash management algorithm assigns a new erase count value instead of the lost one based on either a maximum value, an average value or a value combining the maximum value of the known erase counts and some tolerance value. The known values may be obtained from wear leveling data or from a stored erase history.
摘要翻译：例如由于电源故障而丢失的闪速存储器块的擦除计数被更新或者通过使用闪存的其它块的已知擦除计数来代替。闪存管理算法基于最大值，平均值或组合已知擦除计数的最大值和某个公差值的值来分配新的擦除计数值而不是丢失计数值。可以从磨损均衡数据或从存储的擦除历史获得已知值。

20. 发明授权

US07923757B2 Semiconductor device and associated layouts having linear shaped gate electrodes defined along at least five adjacent gate electrode tracks of equal pitch with gate electrode connection through single interconnect level 有权
标题翻译：半导体器件和相关布局具有沿着至少五个相等间距的栅极电极限定的线形栅电极，栅电极连接通过单互连级
公开(公告)号：US07923757B2
公开(公告)日：2011-04-12
申请号：US12563066
申请日：2009-09-18
申请人： Scott T. Becker , Michael C. Smayling
发明人： Scott T. Becker , Michael C. Smayling
IPC分类号： H01L27/10
CPC分类号： H01L27/11807 , G06F17/5068 , G06F17/5072 , H01L21/28123 , H01L21/823871 , H01L23/5226 , H01L23/5283 , H01L27/0207 , H01L27/088 , H01L27/092 , H01L29/42372 , H01L29/42376 , H01L2027/11812 , H01L2027/11814 , H01L2027/11855 , H01L2027/11861 , H01L2027/11862 , H01L2027/11864 , H01L2027/11866 , H01L2027/11875 , H01L2027/11887 , H01L2027/11888 , H01L2924/0002 , H01L2924/00
摘要： A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.
摘要翻译：限制布局区域包括扩散级别布局，包括由中心非活动区域分隔的p型和n型扩散区域布局形状。扩散区域布局形状相对于被定义为平分扩散级布局的中心线以非对称的方式定义。栅极电极层布局被定义为包括仅在第一平行方向上延伸的线性布局特征。在第一并行方向上共享共同的范围的相邻的线性布局特征被跨越栅电极级布局基本上相等的端到端间隔隔开，并且被最小化到半导体器件允许的程度制造能力。栅电极级布局包括沿着沿着第一并行方向的至少四个不同的线段限定的线性布局特征。限制布局区域对应于单元布局的整个栅电极层。

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