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151. 发明申请

US20050104117A1 Charge-trapping memory device and methods for operating and manufacturing the cell 有权
标题翻译：电荷捕获存储器件以及用于操作和制造电池的方法
公开(公告)号：US20050104117A1
公开(公告)日：2005-05-19
申请号：US10715142
申请日：2003-11-17
申请人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
发明人： Thomas Mikolajick , Hans Reisinger , Josef Willer , Corvin Liaw
IPC分类号： G11C16/04 , H01L21/28 , H01L21/8246 , H01L27/115 , H01L29/792 , H01L29/788
CPC分类号： H01L27/11568 , G11C16/0466 , G11C16/0491 , H01L21/28282 , H01L27/115 , H01L29/7923
摘要： The charge-trapping layer comprises two strips above the source and drain junctions. The thicknesses of the charge-trapping layer and the gate dielectric are chosen to facilitate Fowler-Nordheim-tunnelling of electrons into the strips during an erasure process. Programming is performed by injection of hot holes into the strips individually for two-bit storage.
摘要翻译：电荷捕获层包括在源极和漏极结上方的两个条带。选择电荷俘获层和栅极电介质的厚度，以便在擦除过程中促进Fowler-Nordheim隧穿隧道的电子。通过将热孔单独注入热孔进行两位存储来执行编程。

152. 发明申请

US20050045935A1 Semiconductor memory having charge trapping memory cells 失效
标题翻译：具有电荷捕获存储单元的半导体存储器
公开(公告)号：US20050045935A1
公开(公告)日：2005-03-03
申请号：US10890803
申请日：2004-07-14
申请人： Josef Willer , Christoph Ludwig , Joachim Deppe
发明人： Josef Willer , Christoph Ludwig , Joachim Deppe
IPC分类号： H01L21/8247 , H01L21/8246 , H01L27/115 , H01L29/788 , H01L29/792 , H01L27/108
CPC分类号： H01L27/11568 , H01L27/115
摘要： In a charge trapping memory architecture for virtual ground with interconnects (6) that are present parallel to the word lines (2) and STI isolations (1) that are present parallel to the bit lines (4), provision is made of STI isolations (7) that are widened for division into slices. Instead of this, the interconnects present below a bit line may be omitted or two mutually adjacent bit lines (41, 42) may be wired up in such a way that the memory transistors present between them operate only in the dummy mode.
摘要翻译：在具有与字线（2）并行存在的互连（6）的虚拟接地的电荷捕获存储器架构中，并行于位线（4）的STI隔离（1），提供STI隔离（ 7）被分割成切片。而不是这样，存在于位线下方的互连可以被省略，或者两个相互相邻的位线（41,42）可以以使得它们之间存在的存储晶体管仅在虚拟模式中操作的方式被布线。

153. 发明授权

US06664612B2 Semiconductor component having double passivating layers formed of two passivating layers of different dielectric materials 失效
标题翻译：半导体元件具有由两种不同介电材料的钝化层形成的双钝化层
公开(公告)号：US06664612B2
公开(公告)日：2003-12-16
申请号：US09757328
申请日：2001-01-09
申请人： Josef Willer , Paul-Werner Von Basse , Thomas Scheiter
发明人： Josef Willer , Paul-Werner Von Basse , Thomas Scheiter
IPC分类号： H01L2358
CPC分类号： G06K9/0002 , H01L21/3145
摘要： A semiconductor component with passivation includes at least two double passivating layers, of which an uppermost is applied to a planar surface of a layer located therebelow. The double passivating layers include two layers of different dielectric materials, for example silicon oxide and silicon nitride. The respective thicknesses of the individual passivating layers can be adapted to dimensions of the structuring of the layer to which the passivation is applied. This produces a reliable passivation which is particularly suitable for capacitively measuring fingerprint sensors.
摘要翻译：具有钝化的半导体部件包括至少两个双钝化层，其中最上层被施加到位于其下方的层的平坦表面。双钝化层包括两层不同的介电材料，例如氧化硅和氮化硅。单个钝化层的各自的厚度可以适应于施加钝化层的层的结构尺寸。这产生了可靠的钝化，其特别适用于电容测量指纹传感器。

154. 发明授权

US06642565B2 Miniaturized capacitor with solid-state dielectric, in particular for integrated semiconductor memories, E.G. DRAMS, and method for fabricating such a capacitor 有权
公开(公告)号：US06642565B2
公开(公告)日：2003-11-04
申请号：US09935624
申请日：2001-08-23
申请人： Emmerich Bertagnolli , Till Schlösser , Josef Willer
发明人： Emmerich Bertagnolli , Till Schlösser , Josef Willer
IPC分类号： H01L27108
CPC分类号： H01L28/82
摘要： A dynamic random access memory capacitor and to a method for producing the same are described. A first (bottom) electrode of the capacitor has a grained surface made of tungsten silicide placed on a tungsten silicide layer which is disposed near a surface of a electrode body. The graining of the tungsten silicide layer is formed by tempering a temporarily present double layer that is formed of an understoichiometric tungsten silicide layer and a silicon layer. The double layer is formed on the tungsten silicide layer.

155. 发明授权

US06566187B1 DRAM cell system and method for producing same 有权
标题翻译： DRAM单元系统及其制造方法
公开(公告)号：US06566187B1
公开(公告)日：2003-05-20
申请号：US09806614
申请日：2001-05-11
申请人： Josef Willer , Franz Hoffmann , Till Schlösser
发明人： Josef Willer , Franz Hoffmann , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F2.
摘要翻译： DRAM单元布置及其制造方法字线和位线布置在基板的主区域上方，结果是它们具有平面结构，并且可以与单元布置的外围的晶体管的栅电极一起生成。每个存储单元提供基板的凹陷，存储电容器的存储节点布置在所述凹陷的下部区域中，并且垂直晶体管的栅电极布置在所述凹陷的上部区域中。存储单元的凹陷布置在填充有隔离结构的沟槽之间。晶体管的上部源极/漏极区域布置在两个相互相邻的隔离结构之间以及两个彼此相邻的凹陷之间。下部源极/漏极区域布置在衬底中并与存储节点相邻。对于工艺步骤，对准公差如此大，使得存储器单元的空间需求可以达到4F2。

156. 发明授权

US06548350B2 Method of fabricating an integrated circuit configuration with at least one capacitor 有权
公开(公告)号：US06548350B2
公开(公告)日：2003-04-15
申请号：US10093039
申请日：2002-03-07
申请人： Bernhard Sell , Dirk Schumann , Josef Willer
发明人： Bernhard Sell , Dirk Schumann , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L27/10852
摘要： The capacitor is arranged on the surface of a substrate. A first capacitor electrode has a middle part and a side part, which point vertically upwards, are arranged beside each other and are connected with each other via an upper part located above said middle part and said side part. The middle part is longer than the side part and is connected with other components of the circuit configuration located below said middle part and said side part. The first capacitor electrode is provided with a capacitor dielectric. A second capacitor electrode borders the capacitor dielectric.

157. 发明授权

US06492221B1 DRAM cell arrangement 有权
标题翻译： DRAM单元布置
公开(公告)号：US06492221B1
公开(公告)日：2002-12-10
申请号：US09806427
申请日：2001-07-03
申请人： Franz Hofmann , Josef Willer , Till Schloesser
发明人： Franz Hofmann , Josef Willer , Till Schloesser
IPC分类号： H01L218244
CPC分类号： H01L27/10864 , H01L27/10841 , H01L27/10876
摘要： A dynamic random access memory includes memory cells arranged in rows and columns on the substrate and a plurality of connecting pillars, each associated with a memory cell. A bit line extends above the main area of the substrate and connects to each memory cell of a column. A first word line connects a first set of alternate memory cells of a row by a first subset of the plurality of connecting pillars. The first word line includes first parts arranged offset relative to the first subset of connecting pillars. A strip-shaped second part extends above the main area and adjoins the first parts of the first word line. A second word line connects to a second set of alternate memory cells of the row by a second subset of the connecting pillars. The second word line includes first parts arranged between mutually adjacent first word lines and offset from the second subset of the connecting pillars. Both the first and second word lines thus overlap but do not cover the connecting pillars. A strip-shaped second part extends above the main area in the first direction and adjoins the first parts of the second word line. The second part is above the first word line and the bit line.
摘要翻译：动态随机存取存储器包括以衬底上的行和列布置的存储器单元和多个连接柱，每个连接柱与存储单元相关联。位线延伸到基板的主区域上方，并连接到列的每个存储单元。第一字线将一行的第一组备用存储单元与多个连接柱的第一子集连接。第一字线包括相对于连接柱的第一子集排列的第一部分。带状第二部分在主区域的上方延伸并与第一字线的第一部分邻接。第二字线通过连接柱的第二子集连接到该行的第二组替代存储器单元。第二字线包括布置在彼此相邻的第一字线之间的第一部分和与连接柱的第二子集的偏移。因此，第一和第二字线都重叠，但不覆盖连接柱。带状第二部分沿着第一方向延伸到主区域上方并与第二字线的第一部分相邻。第二部分在第一个字线和位线之上。

158. 发明授权

US06448600B1 DRAM cell configuration and fabrication method 失效
标题翻译： DRAM单元配置和制造方法
公开(公告)号：US06448600B1
公开(公告)日：2002-09-10
申请号：US09713484
申请日：2000-11-15
申请人： Till Schlösser , Franz Hofmann , Josef Willer
发明人： Till Schlösser , Franz Hofmann , Josef Willer
IPC分类号： H01L218242
CPC分类号： H01L27/10867 , H01L27/10876 , H01L27/10888
摘要： The memory cells each have a capacitor and a transistor. A storage node of the capacitor is arranged in a first depression formed in a substrate. A gate electrode of the transistor is arranged in a second depression at a first lateral surface of the second depression. The second depression is spaced apart from the first depression. An upper source/drain region of the transistor adjoins the storage node and the second depression. A lower source/drain region of the transistor is formed deeper in the substrate than the upper source/drain region and it adjoins the second depression.
摘要翻译：存储单元各自具有电容器和晶体管。电容器的存储节点布置在形成在基板中的第一凹部中。晶体管的栅极布置在第二凹陷处的第二凹陷处的第二凹陷处的第一侧表面处。第二凹陷与第一凹陷间隔开。晶体管的上源极/漏极区域与存储节点和第二凹陷相邻。晶体管的下源极/漏极区域在衬底中比上部源极/漏极区域形成得更深，并且与第二凹陷相邻。

159. 发明授权

US06442065B1 Method for operating a memory cell configuration having dynamic gain memory cells 有权
标题翻译：用于操作具有动态增益存储单元的存储单元配置的方法
公开(公告)号：US06442065B1
公开(公告)日：2002-08-27
申请号：US09935356
申请日：2001-08-22
申请人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
发明人： Franz Hofmann , Wolfgang Krautschneider , Till Schlösser , Josef Willer
IPC分类号： G11C1140
CPC分类号： G11C11/404 , G11C11/4023
摘要： Each memory cell of a cell configuration includes at least one memory transistor. To write first or second information on the memory cell, a gate electrode of the memory transistor is charged such that a first voltage or a second voltage is applied in the memory transistor. A reading voltage is applied in a second source/drain area of the memory transistor to read first information and second information respectively. The first voltage is applied between the second voltage and the reading voltage. The reading voltage is applied between the first voltage less a threshold voltage of the memory transistor and the second voltage less the threshold voltage of the memory transistor.
摘要翻译：单元结构的每个存储单元包括至少一个存储晶体管。为了在存储单元上写入第一或第二信息，对存储晶体管的栅电极进行充电，使得在存储晶体管中施加第一电压或第二电压。在存储晶体管的第二源极/漏极区域中施加读取电压以分别读取第一信息和第二信息。第一电压施加在第二电压和读取电压之间。读取电压施加在较低存储晶体管的阈值电压的第一电压和小于存储晶体管的阈值电压的第二电压之间。

160. 发明授权

US06403440B1 Method for fabricating a stacked capacitor in a semiconductor configuration, and stacked capacitor fabricated by this method 有权
标题翻译：用于制造半导体结构中的叠层电容器的方法和通过该方法制造的层叠电容器
公开(公告)号：US06403440B1
公开(公告)日：2002-06-11
申请号：US09285897
申请日：1999-04-08
申请人： Emmerich Bertagnolli , Josef Willer
发明人： Emmerich Bertagnolli , Josef Willer
IPC分类号： H01L2120
CPC分类号： H01L28/87 , H01L27/10852 , H01L28/88
摘要： A method for fabricating a stacked capacitor in a semiconductor configuration, in which one electrode of the stacked capacitor is connected via a terminal region of a first conductivity type to a source or drain of a transistor. The semiconductor configuration having one electrode of a stacked capacitor produced by utilizing different etching rates of semiconductor layers of a second conductivity type which are doped to different extents. After the etching of the one electrode of the stacked capacitor, doping reversal of the semiconductor layers remaining after the etching operation to the first conductivity type is performed, with the result that the electrode has the same conductivity type as the terminal region and no pn junction occurs between the electrode and terminal region.
摘要翻译：一种用于制造半导体构造的层叠电容器的方法，其中层叠电容器的一个电极经由第一导电类型的端子区域连接到晶体管的源极或漏极。半导体结构具有通过利用掺杂到不同程度的第二导电类型的半导体层的不同蚀刻速率而产生的堆叠电容器的一个电极。在层叠电容器的一个电极的蚀刻之后，执行在蚀刻操作之后保留的半导体层的掺杂反转到第一导电类型，结果是电极具有与端子区域相同的导电类型，并且没有pn结发生在电极和端子区域之间。

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