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1. 发明授权

US06566187B1 DRAM cell system and method for producing same 有权
标题翻译： DRAM单元系统及其制造方法
公开(公告)号：US06566187B1
公开(公告)日：2003-05-20
申请号：US09806614
申请日：2001-05-11
申请人： Josef Willer , Franz Hoffmann , Till Schlösser
发明人： Josef Willer , Franz Hoffmann , Till Schlösser
IPC分类号： H01L218242
CPC分类号： H01L27/10864 , H01L27/10841
摘要： DRAM cell arrangement and method for fabricating it Word lines and bit lines are arranged above a main area of a substrate, with the result that they have a planar construction and can be produced together with gate electrodes of transistors of a periphery of the cell arrangement. A depression of the substrate is provided per memory cell, a storage node of a storage capacitor being arranged in the lower region of said depression and a gate electrode of a vertical transistor being arranged in the upper region of said depression. The depressions of the memory cells are arranged between trenches filled with isolating structures. Upper source/drain regions of the transistors are arranged between two mutually adjacent isolating structures and between two mutually adjacent depressions. Lower source/drain regions are arranged in the substrate and adjoin the storage nodes. For process steps, alignment tolerances are so large that the space requirement for the memory cell can amount to 4F2.
摘要翻译： DRAM单元布置及其制造方法字线和位线布置在基板的主区域上方，结果是它们具有平面结构，并且可以与单元布置的外围的晶体管的栅电极一起生成。每个存储单元提供基板的凹陷，存储电容器的存储节点布置在所述凹陷的下部区域中，并且垂直晶体管的栅电极布置在所述凹陷的上部区域中。存储单元的凹陷布置在填充有隔离结构的沟槽之间。晶体管的上部源极/漏极区域布置在两个相互相邻的隔离结构之间以及两个彼此相邻的凹陷之间。下部源极/漏极区域布置在衬底中并与存储节点相邻。对于工艺步骤，对准公差如此大，使得存储器单元的空间需求可以达到4F2。

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