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141. 发明授权

US06486540B2 Three-dimensional semiconductor device and method of manufacturing the same 有权
标题翻译：三维半导体器件及其制造方法
公开(公告)号：US06486540B2
公开(公告)日：2002-11-26
申请号：US09829945
申请日：2001-04-11
申请人： Naoji Senba , Takao Yamazaki , Yuzo Shimada
发明人： Naoji Senba , Takao Yamazaki , Yuzo Shimada
IPC分类号： H01L2302
CPC分类号： H01L23/34 , H01L25/0652 , H01L2924/0002 , H01L2924/00
摘要： A three-dimensional semiconductor device includes a cylindrical heat sink, wherein a CPU is provided on a substantially center of an inner bottom surface of the cylindrical heat sink, semiconductor chips are respectively mounted on an outer peripheral surface and an inner peripheral surface of the cylindrical heat sink, and the CPU is connected to an upper heat sink.
摘要翻译：三维半导体器件包括圆柱形散热器，其中CPU设置在圆柱形散热器的内底表面的大致中心上，半导体芯片分别安装在圆柱形散热器的外周表面和圆柱形散热器，CPU连接到上部散热器。

142. 发明授权

US06476476B1 Integrated circuit package including pin and barrel interconnects 有权
标题翻译：集成电路封装，包括引脚和机筒互连
公开(公告)号：US06476476B1
公开(公告)日：2002-11-05
申请号：US09932109
申请日：2001-08-16
申请人： Thomas P. Glenn
发明人： Thomas P. Glenn
IPC分类号： H01L2302
CPC分类号： H05K1/119 , H01L21/563 , H01L23/13 , H01L23/3107 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/105 , H01L2223/6622 , H01L2224/05554 , H01L2224/05571 , H01L2224/05573 , H01L2224/16 , H01L2224/16225 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/49171 , H01L2224/73204 , H01L2225/1005 , H01L2225/1058 , H01L2225/1082 , H01L2924/00014 , H01L2924/01028 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H05K1/144 , H05K3/368 , H05K3/42 , H05K2201/09045 , H05K2201/09118 , H05K2203/167 , H01L2224/05599 , H01L2924/00012 , H01L2924/00
摘要： Stackable integrated circuit packages with pin and barrel interconnects are disclosed, along with methods of making such packages. In an exemplary embodiment, a package includes a molded plastic body, metal coated barrels on an upper side of the body, and metal coated pins on a lower side of the body. The pins are arranged coaxial with respective barrels. An integrated circuit is mounted on the upper side of the body. Metal traces electrically couple the integrated circuit to the barrels. Vias through the body electrically connect the metal coated barrels to respective metal coated pins. Two or more packages may be stacked and electrically coupled together by inserting the pins of a top package into the barrels of a lower package. The pins of the lower package may be soldered to a conventional printed circuit board, or may be mounted on a mounting substrate including corresponding metal coated barrels.
摘要翻译：公开了具有销和桶互连的可堆叠集成电路封装以及制造这种封装的方法。在示例性实施例中，包装包括模制塑料体，在身体的上侧上的金属涂覆的桶和在身体的下侧上的金属涂覆的销。销与相应的桶同轴布置。集成电路安装在主体的上侧。金属迹线将集成电路电耦合到桶。穿过车身的通孔将金属涂层的桶电连接到相应的金属涂层销。可以通过将顶部包装的销插入下部包装的桶中来堆叠并电耦合两个或更多个包装。下封装的引脚可以焊接到传统的印刷电路板上，或者可以安装在包括相应的金属涂覆的滚筒的安装基板上。

143. 发明授权

US06476475B1 Stacked SRAM die package 有权
标题翻译：堆叠SRAM裸片封装
公开(公告)号：US06476475B1
公开(公告)日：2002-11-05
申请号：US09892779
申请日：2001-06-28
申请人： Melissa Siow-Lui Lee
发明人： Melissa Siow-Lui Lee
IPC分类号： H01L2302
CPC分类号： H01L24/83 , H01L24/31 , H01L25/0657 , H01L2224/2919 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/8319 , H01L2224/8385 , H01L2225/0651 , H01L2225/06527 , H01L2225/06575 , H01L2225/06596 , H01L2924/01029 , H01L2924/01033 , H01L2924/014 , H01L2924/0665 , H01L2924/07802 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00
摘要： A circuit assembly is formed with a polyimide coated lower SRAM die and an upper die resin bonded to the SRAM die. The repair access opening in the polyimide coating on the upper surface of the SRAM die is filled with polyimide for protection before attaching the upper die to the SRAM die. Embodiments of the present invention including positioning a solid piece of polyimide within the repair access opening or spraying a thin coating of polyimide over the opening and on the first polyimide coating.
摘要翻译：电路组件形成有聚酰亚胺涂覆的下SRAM模头和粘合到SRAM模具的上模树脂。在SRAM模具的上表面上的聚酰亚胺涂层中的修复进入口在用于保护上模之前填充有聚酰亚胺用于保护。本发明的实施例包括将固体聚酰亚胺块定位在修理进入口内或者在开口上和第一聚酰亚胺涂层上喷涂薄的聚酰亚胺涂层。

144. 发明授权

US06476473B1 Memory module having backup function 失效
标题翻译：具有备份功能的内存模块
公开(公告)号：US06476473B1
公开(公告)日：2002-11-05
申请号：US09537227
申请日：2000-03-28
申请人： A Ping Lu , Chiaki Kato
发明人： A Ping Lu , Chiaki Kato
IPC分类号： H01L2302
CPC分类号： G06F11/1666 , G06F11/1417 , G06F11/20
摘要： The present invention relates to a backup module for a standard memory chip, more especially a standard memory chip (for example, DIP, QFJ and PLCC packages) having high-density pins for the backup of a personal computer. If the standard memory chip is out of order, the backup module according to the present invention can take the place of the standard memory chip. By switching between two or more chips, the capacity of the memory can be effectively increased as a whole and the content (program or data) of the memory can be easily optimized.
摘要翻译：本发明涉及一种用于标准存储器芯片的备用模块，更具体地说，涉及一种具有用于个人计算机备份的高密度引脚的标准存储器芯片（例如，DIP，QFJ和PLCC封装）。如果标准存储器芯片出现故障，则根据本发明的备份模块可以代替标准存储器芯片。通过在两个或更多个芯片之间切换，可以有效地增加存储器的容量，并且可以容易地优化存储器的内容（程序或数据）。

145. 发明授权

US06476472B1 Integrated circuit package with improved ESD protection for no-connect pins 有权
标题翻译：集成电路封装，具有改进的ESD保护，用于无连接引脚
公开(公告)号：US06476472B1
公开(公告)日：2002-11-05
申请号：US09641899
申请日：2000-08-18
申请人： Kerry L. Davison , Donald E. Hawk, Jr. , Yehuda Smooha
发明人： Kerry L. Davison , Donald E. Hawk, Jr. , Yehuda Smooha
IPC分类号： H01L2302
CPC分类号： H01L23/60 , H01L24/48 , H01L24/49 , H01L2224/05553 , H01L2224/05599 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/48233 , H01L2224/49171 , H01L2224/85399 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/00 , H01L2224/45015 , H01L2924/207 , H01L2924/00012
摘要： An integrated circuit (IC) package includes an IC having at least one ESD protection circuit that provides protection against electrostatic discharge. The IC has a plurality of bond pads that are not coupled to the ESD protection circuit. The IC is connected to a substrate. The substrate has a first plurality of conductive traces, which are connected to respective bond pads of the IC, and a second plurality of conductive traces, which are not connected to any of the plurality of bond pads of the IC. Either the substrate or the IC has a common conductive trace that is connected to the ESD protection circuit. Each of the second plurality of conductive traces is connected to the common conductive trace.
摘要翻译：集成电路（IC）封装包括具有至少一个ESD保护电路的IC，其提供防止静电放电的保护。 IC具有多个不连接到ESD保护电路的接合焊盘。 IC连接到基板。衬底具有连接到IC的相应接合焊盘的第一多个导电迹线和不连接到IC的多个接合焊盘中的任一个的第二多个导电迹线。衬底或IC都具有连接到ESD保护电路的公共导电迹线。第二多个导电迹线中的每一个连接到公共导电迹线。

146. 发明授权

US06472736B1 Stacked structure for memory chips 有权
标题翻译：内存芯片的堆叠结构
公开(公告)号：US06472736B1
公开(公告)日：2002-10-29
申请号：US10097822
申请日：2002-03-13
申请人： Nai Hua Yeh , Chen Pin Peng
发明人： Nai Hua Yeh , Chen Pin Peng
IPC分类号： H01L2302
CPC分类号： H01L25/0657 , H01L23/3128 , H01L23/5385 , H01L24/48 , H01L2224/05599 , H01L2224/06136 , H01L2224/32145 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/4824 , H01L2224/73215 , H01L2224/73265 , H01L2224/85399 , H01L2225/0651 , H01L2225/06527 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/15311 , H01L2924/181 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A stacked structure for memory chips includes a substrate, a lower memory chip, an upper memory chip, and an insulation medium. The substrate has an upper surface, a lower surface and a slot penetrating through the substrate from the upper surface to the lower surface. The lower memory chip has a central portion formed with a plurality of bonding pads. The lower memory chip is arranged on the upper surface of the substrate. The plurality of bonding pads is exposed via the slot of the substrate, and the bonding pads are electrically connected to the lower surface of the substrate via a plurality of wires. The upper memory chip has a central portion formed with a plurality of bonding pads. The upper memory chip is arranged on the lower memory chip in a back-to-back manner with respect to the lower memory chip so that the plurality of bonding pads of the upper memory chip faces upwards. The insulation medium has a central portion formed with a slot. The plurality of bonding pads of the upper memory chip is exposed via the slot of the insulation medium. The insulation medium is formed with a plurality of traces electrically connecting to the bonding pads of the upper memory chip and the upper surface of the substrate via a plurality of wires. Accordingly, the length and radian of each wire can be reduced so that a better signal transmission effect and a smaller package volume can be obtained.
摘要翻译：用于存储芯片的叠层结构包括基板，下存储芯片，上存储芯片和绝缘介质。基板具有从上表面到下表面穿过基板的上表面，下表面和狭槽。下部存储器芯片具有形成有多个接合焊盘的中心部分。下部存储器芯片布置在基板的上表面上。多个接合焊盘经由衬底的槽暴露，并且焊盘通过多根电线电连接到衬底的下表面。上存储芯片具有形成有多个接合焊盘的中心部分。上部存储器芯片相对于下部存储器芯片以背靠背的方式布置在下部存储器芯片上，使得上部存储器芯片的多个焊盘面朝上。绝缘介质具有形成有槽的中心部分。上存储芯片的多个接合焊盘通过绝缘介质的槽露出。绝缘介质形成有多条迹线，其经由多根电线电连接到上存储芯片的接合焊盘和衬底的上表面。因此，可以减少每条线的长度和弧度，从而可以获得更好的信号传输效果和更小的封装体积。

147. 发明授权

US06469377B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06469377B1
公开(公告)日：2002-10-22
申请号：US09842938
申请日：2001-04-25
申请人： Yoichiro Kondo
发明人： Yoichiro Kondo
IPC分类号： H01L2302
CPC分类号： H01L23/5382 , H01L23/5387 , H01L25/0657 , H01L2224/16 , H01L2225/06575 , H01L2225/06579 , H01L2225/06586 , H05K1/189
摘要： To provide a semiconductor device with a three-dimensional mounting module using a flexible circuit substrate which is easy to assemble a three-dimensional structure and is excellent in the workability in repair work (or re-work). [MEANS FOR SOLUTION] A flexible circuit substrate 11 has mounting regions 111, 112 and 113 on which electronic components 121, 122 and 123 are mainly mounted, respectively, and other electronic components 124 and 125 are also mounted. The flexible circuit substrate 11 is structured in such a manner that the mounting regions 111˜113 are folded on top of the other over the base region 110 in a predetermined order (f1˜f3). An integrated spacer 13 has thick regions 131 and thin regions 132, and is superposed and affixed to the flexible circuit substrate 11 as indicated by arrows with broken lines, and supports the electronic components 121˜125 stacked in layers. Fixing bosses 134 and aperture sections 14 to be coupled therewith are provided to facilitate positioning.
摘要翻译：为了使半导体器件具有使用容易组装三维结构的柔性电路基板的三维安装模块，并且在维修工作（或重新加工）中的可操作性优异。[用于解决方案]柔性电路基板11具有安装区域111,112和113，其上主要安装有电子部件121,122和123，并且还安装了其他电子部件124和125。柔性电路基板11的结构使得安装区域111〜113以预定顺序（f1〜f3）折叠在基部区域110上。集成隔离物13具有厚区域131和薄区域132，并且如虚线箭头所示地叠置并固定到柔性电路基板11，并且支撑层叠的电子部件121〜125。固定凸台134和与其联接的孔部分14被提供以便于定位。

148. 发明授权

US06469371B2 Non-contact type IC card and process for manufacturing same 失效
标题翻译：非接触式IC卡及其制造方法
公开(公告)号：US06469371B2
公开(公告)日：2002-10-22
申请号：US09745707
申请日：2000-12-21
申请人： Masatoshi Akagawa
发明人： Masatoshi Akagawa
IPC分类号： H01L2302
CPC分类号： G06K19/0775 , G06K19/07749 , H01L2224/16 , H01L2924/01078 , H01L2924/01079 , H05K3/4685 , Y10T29/49018 , Y10T29/4902 , Y10T29/4913
摘要： A non-contact type IC card includes an insulating film having first and second surfaces. A plane coil is arranged on the first surface of the film. A semiconductor element is arranged on the first surface of the filmy The film has through holes which expose terminals of the plane coil and electrode terminals of the semiconductor element to the second surface of the film. A wiring pattern consisting of conductive paste is filled in the through holes and extends therebetween along the second surface of the film so that the terminals of the plane coil are electrically connected to the electrode terminals of the semiconductor element by means of the wiring pattern.
摘要翻译：非接触型IC卡包括具有第一表面和第二表面的绝缘膜。平面线圈布置在膜的第一表面上。半导体元件布置在膜的第一表面上。膜具有将平面线圈的端子和半导体元件的电极端子暴露于膜的第二表面的通孔。由导电膏组成的布线图案填充在通孔中，沿着膜的第二表面延伸，使得平面线圈的端子通过布线图形电连接到半导体元件的电极端子。

149. 发明授权

US06445064B1 Semiconductor device 失效
标题翻译：双封装半导体器件
公开(公告)号：US06445064B1
公开(公告)日：2002-09-03
申请号：US09906794
申请日：2001-07-18
申请人： Hideki Ishii , Kazunari Michii , Jun Shibata , Moriyoshi Nakashima
发明人： Hideki Ishii , Kazunari Michii , Jun Shibata , Moriyoshi Nakashima
IPC分类号： H01L2302
CPC分类号： H01L23/49575 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L2224/05554 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/49171 , H01L2224/73265 , H01L2225/06551 , H01L2225/06568 , H01L2225/1011 , H01L2225/1029 , H01L2924/01078 , H01L2924/01079 , H01L2924/10161 , H01L2924/10162 , H01L2924/14 , H01L2924/15153 , H01L2924/15311 , H01L2924/181 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor device includes a first semiconductor package and a second semiconductor package which is mounted onto the first semiconductor package. The first semiconductor package has lands on an upper surface for mounting the second semiconductor package and lands on the lower surface for external connection, which are used for connection with a mounting substrate. The second semiconductor package has external leads which are connected to the lands for mounting the second semiconductor package.
摘要翻译：半导体器件包括安装在第一半导体封装上的第一半导体封装和第二半导体封装。第一半导体封装具有用于安装第二半导体封装的上表面的平台，并且用于与安装基板连接的用于外部连接的下表面。第二半导体封装具有连接到用于安装第二半导体封装的焊盘的外部引线。

150. 发明授权

US06445062B1 Semiconductor device having a flip chip cavity with lower stress and method for forming same 失效
标题翻译：具有具有较低应力的倒装芯片腔的半导体器件及其形成方法
公开(公告)号：US06445062B1
公开(公告)日：2002-09-03
申请号：US09506139
申请日：2000-02-17
申请人： Hirokazu Honda
发明人： Hirokazu Honda
IPC分类号： H01L2302
CPC分类号： H01L23/564 , H01L21/50 , H01L21/54 , H01L21/563 , H01L23/055 , H01L23/49816 , H01L2224/16 , H01L2224/73203 , H01L2224/73204 , H01L2224/73253 , H01L2924/00014 , H01L2924/12044 , H01L2924/15311 , H01L2924/16151 , H01L2924/16195 , H01L2924/3511 , H01L2224/0401
摘要： There is provided a semiconductor device including (a) a substrate, (b) a semiconductor chip mounted on the substrate, (c) a wall having a closed cross-section and mounted on the substrate such that the semiconductor chip is surrounded by the wall, and (d) a cover covering the wall therewith so that a closed cavity is defined by the substrate, the wall and the cover, the cavity being designed to be under a pressure almost equal to an atmospheric pressure at a temperature highest in both steps of fabricating the semiconductor device and steps expectable after the semiconductor device is completed. The semiconductor device can prevent defectiveness such as electric leakage and electromigration, and further prevent occurrence of “popcorn” phenomenon which might occur in an annealing step.
摘要翻译：提供了一种半导体器件，包括（a）衬底，（b）安装在衬底上的半导体芯片，（c）具有闭合截面的壁，并安装在衬底上，使得半导体芯片被壁围，和（d）覆盖其壁的盖，使得由基底，壁和盖限定封闭的空腔，空腔被设计成在两个步骤中最高的温度下几乎等于大气压的压力制造半导体器件和在半导体器件完成之后期望的步骤。半导体器件可以防止诸如漏电和电迁移的缺陷，并且进一步防止在退火步骤中可能发生的“爆米花”现象的发生。

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