专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

141. 发明申请

US20080002448A1 Semiconductor integrated circuit 有权
标题翻译：半导体集成电路
公开(公告)号：US20080002448A1
公开(公告)日：2008-01-03
申请号：US11896802
申请日：2007-09-06
申请人： Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
发明人： Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
IPC分类号： G11C5/06
CPC分类号： G11C7/02 , G11C5/06 , G11C5/063 , G11C8/08 , G11C8/14 , G11C11/408 , G11C11/4085 , G11C11/4096 , G11C11/4097 , H01L27/0207 , H01L27/10814 , H01L27/10882
摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.
摘要翻译：在追求微型制造的大规模集成DRAM中，数据线字线耦合电容在配对数据线之间不平衡。数据线字线的不平衡意味着当数据线经受放大时产生大的噪声，这极有可能引起数据线上非常小的信号的恶化和数据的错误放大。连接到连接到一个数据线的多个存储单元的多个字线中的一个或几个字线交替地连接到布置在存储器阵列的相对侧上的子字驱动器阵列。当数据线被放大时，正和负字线噪声分量在子字驱动器中彼此抵消，从而可以减小字线噪声。因此，可以防止由读出放大器读出的信号劣化，从而提高存储器操作的可靠性。

142. 发明授权

US07307906B2 Semiconductor storage device 失效
标题翻译：半导体存储设备
公开(公告)号：US07307906B2
公开(公告)日：2007-12-11
申请号：US11376169
申请日：2006-03-16
申请人： Kazuhiko Kajigaya
发明人： Kazuhiko Kajigaya
IPC分类号： G11C7/02
CPC分类号： G11C11/4097 , G11C11/406 , G11C11/40607
摘要： A semiconductor storage device for storing data to unit blocks of a memory cell array, comprising: two rows of sense amplifiers arranged on both sides of bit lines and each including sense amplifiers; a switch means for switching a connecting state between one row of sense amplifiers and one side of bit lines and switching a connecting state between the other row of sense amplifiers and the other side of bit lines; a control means which sets at least one row of sense amplifiers as a cache memory, and when performing refresh operation of the unit block where row of sense amplifiers to be used as cache memory holds data, controls switch means so that the row of sense amplifiers used as cache memory is disconnected from bit lines and only the row of sense amplifiers not used as said cache memory is used in refresh operation.
摘要翻译：一种用于将数据存储到存储单元阵列的单元块的半导体存储装置，包括：布置在位线两侧并且每个包括读出放大器的两行读出放大器; 切换装置，用于切换一行读出放大器和位线的一侧之间的连接状态，并切换另一行读出放大器与位线的另一侧之间的连接状态; 控制装置，其将至少一行读出放大器设置为高速缓冲存储器，并且当执行要用作高速缓冲存储器的读出放大器行保持数据的单位块的刷新操作时，控制开关装置，使得行的读出放大器用作高速缓冲存储器与位线断开，并且在刷新操作中仅使用未用作所述高速缓冲存储器的读出放大器行。

143. 发明授权

US07304910B1 Semiconductor memory device with sub-amplifiers having a variable current source 有权
标题翻译：具有具有可变电流源的子放大器的半导体存储器件
公开(公告)号：US07304910B1
公开(公告)日：2007-12-04
申请号：US11467793
申请日：2006-08-28
申请人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
IPC分类号： G11C8/18 , G11C5/14
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
摘要翻译：提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。在每个子放大器SAMP中设置有能够根据读使能信号RD1，RD2设定两种电流之一的电流控制电路IC。在定时控制器的控制下，在与脉冲串读取操作中的周期数相对应的定时，生成读使能信号RD 1，RD 2。电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD 1被设置为较大，而当前控制电路IC中的电流被下一个的RD 2设置得较小时，随后的突发读取周期。因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

144. 发明申请

US20070147152A1 Sense amplifier for semiconductor memory device 有权
标题翻译：用于半导体存储器件的检测放大器
公开(公告)号：US20070147152A1
公开(公告)日：2007-06-28
申请号：US11706409
申请日：2007-02-15
申请人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Miyatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/02
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
摘要翻译：本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

145. 发明授权

US07193884B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07193884B2
公开(公告)日：2007-03-20
申请号：US11280170
申请日：2005-11-17
申请人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.
摘要翻译：从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压晶体管经由存储单元晶体管写入电容器的存储节点。此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

146. 发明申请

US20070038919A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070038919A1
公开(公告)日：2007-02-15
申请号：US11495550
申请日：2006-07-31
申请人： Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C29/00
CPC分类号： G06F11/1044 , G11C2029/0409
摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.
摘要翻译：提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。通过这种方式，可以更换制造过程中发生的错误。此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。

147. 发明申请

US20060250876A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20060250876A1
公开(公告)日：2006-11-09
申请号：US11483649
申请日：2006-07-11
申请人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Masayuki Nakamura , Sadayuki Ohkuma , Kazuhiko Kajigaya , Yoshinobu Nakagome
IPC分类号： G11C5/14
CPC分类号： G11C5/063 , G11C5/14 , G11C5/147 , G11C7/1072 , G11C8/12 , G11C11/406 , G11C11/40615 , G11C11/40618 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A synchronous DRAM is provided which includes arrangements for operations of power supply circuitry based upon whether the DRAM is in a power down mode or not. In one embodiment, a first power supply circuit and a second power supply circuit are provided which both receive externally supplied voltages and output internal supply voltages. The first power supply circuit is not in operation when a semiconductor device of the synchronous DRAM is in a power down mode. However, the second power supply circuit is continuously in operation during the power down mode. In another arrangement, the operation of a voltage limiter circuit is controlled based on whether or not the DRAM is in a power down mode.
摘要翻译：提供了一种同步DRAM，其包括基于DRAM是否处于掉电模式的电源电路的操作的布置。在一个实施例中，提供了第一电源电路和第二电源电路，其接收外部提供的电压并输出内部电源电压。当同步DRAM的半导体器件处于掉电模式时，第一电源电路不工作。然而，第二电源电路在掉电模式期间连续运行。在另一种布置中，基于DRAM是否处于断电模式来控制限压器电路的操作。

148. 发明申请

US20060126400A1 Semiconductor integrated circuit 有权
公开(公告)号：US20060126400A1
公开(公告)日：2006-06-15
申请号：US11349918
申请日：2006-02-09
申请人： Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
发明人： Tomonori Sekiguchi , Riichiro Takemura , Kazuhiko Kajigaya , Katsutaka Kimura , Tsugio Takahashi
IPC分类号： G11C7/10
CPC分类号： G11C7/02 , G11C5/06 , G11C5/063 , G11C8/08 , G11C8/14 , G11C11/408 , G11C11/4085 , G11C11/4096 , G11C11/4097 , H01L27/0207 , H01L27/10814 , H01L27/10882
摘要： In a large scale integrated DRAM in pursuit of micro fabrication, data line-word line coupling capacitances are unbalanced between paired data lines. An imbalance in data line-word line means generation of large noise when the data lines are subjected to amplification, which is highly likely invite deterioration of very small signals on the data lines and erroneous amplification of data. One or a few each of a plurality of word lines connected to a plurality of memory cells connected to one data line are alternately connected to subword driver arrays arranged on the opposing sides of a memory array. Positive and negative word line noise components cancel each other in the subword drivers when the data lines are subjected to amplification, so that the word line noise can be reduced. Therefore, signals read out by sense amplifiers can be prevented from deterioration thereby to increase the reliability of memory operation.

149. 发明授权

US07016236B2 Semiconductor memory device and defect remedying method thereof 失效
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US07016236B2
公开(公告)日：2006-03-21
申请号：US11101504
申请日：2005-04-08
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C16/04
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： A semiconductor memory device formed on a semiconductor chip comprises a plurality of first memory arrays, a plurality of second memory arrays, a first voltage generator, and a plurality of first bonding pads. The semiconductor chip is divided into a first rectangle region, a second rectangle region, and a third rectangle region and the third rectangle region is arranged between the first rectangle region and the second rectangle region. The plurality of first memory arrays are formed in the first rectangle region. The plurality of second memory arrays are formed in the second rectangle region. The voltage generator and the plurality of first bonding pads are arranged in the third rectangle region. The plurality of first bonding pads are arranged between the first rectangle region and the voltage generator and no bonding pads are arranged between the voltage generator and the plurality of second memory arrays.
摘要翻译：形成在半导体芯片上的半导体存储器件包括多个第一存储器阵列，多个第二存储器阵列，第一电压发生器和多个第一焊盘。半导体芯片被分成第一矩形区域，第二矩形区域和第三矩形区域，并且第三矩形区域被布置在第一矩形区域和第二矩形区域之间。多个第一存储器阵列形成在第一矩形区域中。多个第二存储器阵列形成在第二矩形区域中。电压发生器和多个第一接合焊盘被布置在第三矩形区域中。多个第一接合焊盘布置在第一矩形区域和电压发生器之间，并且在电压发生器和多个第二存储器阵列之间没有布置接合焊盘。

150. 发明申请

US20060034133A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060034133A1
公开(公告)日：2006-02-16
申请号：US10534049
申请日：2002-11-08
申请人： Tomonori Sekiguchi , Shinichi Myatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Shinichi Myatake , Takeshi Sakata , Riichiro Takemura , Hiromasa Noda , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C7/062 , G11C5/063 , G11C7/065 , G11C7/08 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/18 , G11C8/08 , G11C11/4087 , G11C11/4091 , G11C11/4094 , G11C11/4096 , G11C11/4097 , G11C29/1201 , G11C2207/002 , G11C2207/005 , H01L27/0207 , H01L27/10814 , H01L27/10882 , H01L27/10897
摘要： A direct sense amplifier of the present invention incorporates and isolates: an MOS transistor serving as a differential pair and having a gate connected to a bit line; and an MOS transistor controlled by a column select line wired between RLIO lines in a bit-line direction, and further connects a source of the MOS transistor serving as the differential pair to a common source line wired in the word-line direction. Since the direct sense amplifier only in a select map is activated by the column select line and the common source line during an read operation, power consumption is significantly reduced during the read operation. Also, since a parasitic capacitance of the MOS transistor serving as the differential pair is separated from the local IO line, a load capacity of the local IO line is reduced and the read operation is speeded up. In addition, during the read operation, a data pattern dependency of the load capacity of the local IO line is reduced and a post-manufacture test is easily made.
摘要翻译：本发明的直接感测放大器结合并隔离：用作差分对并具有连接到位线的栅极的MOS晶体管; 以及通过在位线方向上的RLIO线之间布线的列选择线控制的MOS晶体管，并且还将用作差分对的MOS晶体管的源极连接到在字线方向上布线的公共源极线。由于在读取操作期间，仅在选择映射中的直接读出放大器被列选择线和公共源极线激活，所以在读取操作期间功耗显着降低。此外，由于用作差分对的MOS晶体管的寄生电容与本地IO线分离，所以本地IO线的负载容量减小，读取操作加快。此外，在读取操作期间，本地IO线的负载能力的数据模式相关性降低，并且容易进行后期制造测试。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式