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141. 发明申请

US20140035617A1 SPIN TRANSFER TORQUE BASED MEMORY ELEMENTS FOR PROGRAMMABLE DEVICE ARRAYS 有权
标题翻译：用于可编程器件阵列的基于转子扭矩的记忆元件
公开(公告)号：US20140035617A1
公开(公告)日：2014-02-06
申请号：US13997962
申请日：2012-03-30
申请人： Arijit Raychowdhury , James W. Tschanz , Vivek De
发明人： Arijit Raychowdhury , James W. Tschanz , Vivek De
IPC分类号： H03K19/177
CPC分类号： H03K19/17728 , G11C11/16 , H03K19/177
摘要： Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.
摘要翻译：这里公开了使用基于高密度旋转转矩（STT）的存储器元件的半导体器件阵列，诸如现场可编程门阵列（FPGA）和复数可编程逻辑阵列（CPLAs）。基于STT的存储器元件可以是独立的FPGA / CPLAs，或者可以嵌入在微处理器和/或数字信号处理（DSP）片上系统（SoC）中，以提供设计灵活性，以实现低功率，可扩展，安全和可重构硬件架构。由于配置存储在FPGA / CPLA裸片本身，所以每次在外部存储器上加载配置的需求都将在设备通电时被消除。除了即时启动，消除配置I / O流量导致节电和可能的引脚数减少。通过消除将配置数据存储在外部存储器中的需要，安全性大大提高。

142. 发明申请

US20120106285A1 CIRCUITS AND METHODS FOR REDUCING MINIMUM SUPPLY FOR REGISTER FILE CELLS 有权
标题翻译：用于减少寄存器文件的最小供应的电路和方法
公开(公告)号：US20120106285A1
公开(公告)日：2012-05-03
申请号：US13347213
申请日：2012-01-10
申请人： Vivek De , DiaaEldin S. Khalil , Muhammad Khellah , Moty Mehalel , George Shchupak
发明人： Vivek De , DiaaEldin S. Khalil , Muhammad Khellah , Moty Mehalel , George Shchupak
IPC分类号： G11C5/14
CPC分类号： G11C5/142 , G11C5/063 , G11C11/412 , G11C11/413
摘要： A register file employing a shared supply structure to improve the minimum supply voltage.
摘要翻译：采用共享供电结构的寄存器文件来提高最小电源电压。

143. 发明授权

US07776684B2 Increasing the surface area of a memory cell capacitor 有权
标题翻译：增加存储单元电容器的表面积
公开(公告)号：US07776684B2
公开(公告)日：2010-08-17
申请号：US11731193
申请日：2007-03-30
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。第二导电层沉积在第三绝缘层上。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

144. 发明申请

US20100079184A1 Sequential circuit with error detection 有权
标题翻译：具有错误检测的顺序电路
公开(公告)号：US20100079184A1
公开(公告)日：2010-04-01
申请号：US12286067
申请日：2008-09-26
申请人： Keith Bowman , James Tachanz , Nam Sung Kim , Janice Lee , Chris Wilkerson , Shlh-Lian L. Lu , Tanay Kamlk , Vivek De
发明人： Keith Bowman , James Tachanz , Nam Sung Kim , Janice Lee , Chris Wilkerson , Shlh-Lian L. Lu , Tanay Kamlk , Vivek De
IPC分类号： H03K3/037
CPC分类号： H03K3/0375
摘要： Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.
摘要翻译：提供了具有错误检测的顺序电路。例如，它们可以用于替代传统的主从触发器，例如在关键路径电路中，以检测并启动在顺序输入处的后期转换的校正。在一些实施例中，这样的顺序可以包括具有时间借用锁存器的转换检测器。

145. 发明申请

US20080136507A1 ANALOG PHASE CONTROL CIRCUIT AND METHOD 有权
标题翻译：模拟相位控制电路和方法
公开(公告)号：US20080136507A1
公开(公告)日：2008-06-12
申请号：US11609823
申请日：2006-12-12
申请人： Nam Sung Kim , Vivek De
发明人： Nam Sung Kim , Vivek De
IPC分类号： G05F1/10
CPC分类号： H03K19/0016
摘要： In some embodiments, an array of sleep transistors is provided, wherein a combination of said transistors may be enabled during an active mode to reduce leakage depending on the leakage characteristics of a chip or associated chip.
摘要翻译：在一些实施例中，提供了一种睡眠晶体管阵列，其中可以在有源模式期间启用所述晶体管的组合以根据芯片或相关芯片的泄漏特性来减少泄漏。

146. 发明申请

US20070058419A1 Memory cell having p-type pass device 有权
公开(公告)号：US20070058419A1
公开(公告)日：2007-03-15
申请号：US11225912
申请日：2005-09-13
申请人： Muhammad Khellah , Dinesh Somasekhar , Nam Kim , Yibin Ye , Vivek De , Kevin Zhang , Bo Zheng
发明人： Muhammad Khellah , Dinesh Somasekhar , Nam Kim , Yibin Ye , Vivek De , Kevin Zhang , Bo Zheng
IPC分类号： G11C11/00
CPC分类号： G11C11/412 , Y10S257/903
摘要： For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

147. 发明申请

US20070052446A1 DRIVER CIRCUIT 有权
标题翻译：驱动电路
公开(公告)号：US20070052446A1
公开(公告)日：2007-03-08
申请号：US11277117
申请日：2006-03-21
申请人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
发明人： Gerhard Schrom , Peter Hazucha , Jae-Hong Hahn , Vivek De
IPC分类号： H03K19/0175
CPC分类号： H03K17/691 , H03K19/0013
摘要： A circuit includes a first driver, a second driver, and a transformer coupled to the first and second driver. In operation, the first driver receives a first signal from a first input port, the second driver receives a time-delayed version of the first signal from a second input port, and the transformer provides provide an output signal to an output port. A method includes receiving a first input signal, receiving a second input signal, and then processing the first input signal and the second input signal. The second input signal is a time-delayed version of the first input signal and the processing of the first input signal and the second input signal generates a half-raised cosine signal.
摘要翻译：电路包括第一驱动器，第二驱动器和耦合到第一和第二驱动器的变压器。在操作中，第一驱动器从第一输入端口接收第一信号，第二驱动器从第二输入端口接收第一信号的时间延迟版本，并且变压器向输出端口提供输出信号。一种方法包括接收第一输入信号，接收第二输入信号，然后处理第一输入信号和第二输入信号。第二输入信号是第一输入信号的时间延迟版本，第一输入信号和第二输入信号的处理产生半升余弦信号。

148. 发明申请

US20070002607A1 Memory circuit 审中-公开
标题翻译：存储电路
公开(公告)号：US20070002607A1
公开(公告)日：2007-01-04
申请号：US11172078
申请日：2005-06-29
申请人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De
发明人： Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De
IPC分类号： G11C11/00
CPC分类号： G11C11/419
摘要： In some embodiments, a memory array is provided comprising columns of SRAM bit cells, the columns each comprising a bit line and a sense amplifier coupled to the bit line, the sense amplifier to maintain a state in a selected cell of its bit line during a read operation. Other embodiments are disclosed herein.
摘要翻译：在一些实施例中，提供了包括SRAM位单元列的存储器阵列，每个列包括位线和耦合到位线的读出放大器，读出放大器在一段时间内维持其位线的选定单元格中的状态读操作。本文公开了其它实施例。

149. 发明申请

US20060184595A1 Representative majority voter for bus invert coding 有权
标题翻译：代表大多数选民为总线反转编码
公开(公告)号：US20060184595A1
公开(公告)日：2006-08-17
申请号：US11059174
申请日：2005-02-16
申请人： James Tschanz , Mircea Stan , Muhammad Khellah , Yibin Ye , Vivek De
发明人： James Tschanz , Mircea Stan , Muhammad Khellah , Yibin Ye , Vivek De
IPC分类号： G06F15/00
CPC分类号： G06F13/4213 , H03K19/23 , H03M5/145 , Y02D10/14 , Y02D10/151
摘要： In general, in one aspect, the disclosure describes an apparatus inluding a representative majority voter gate to analyze bit transitions of a pluraility of bits. The plurailuty of bits are analzed in groups. The representative majority voter gate generates an invert signal based on the analysis. The apparatus further inludes a conditional inverter to apply the invert signal to the pluraility of bits.
摘要翻译：一般来说，在一个方面，本公开描述了一种包括代表性的多数选民门来分析多个位的位转换的装置。分组的分类分析。代表大多数选民门根据分析产生反转信号。该装置进一步包括条件反相器将反相信号应用于多个位。

150. 发明申请

US20060065962A1 Control circuitry in stacked silicon 审中-公开
标题翻译：堆叠硅中的控制电路
公开(公告)号：US20060065962A1
公开(公告)日：2006-03-30
申请号：US10954256
申请日：2004-09-29
申请人： Siva Narendra , James Tschanz , Vivek De , Shekhar Borkar
发明人： Siva Narendra , James Tschanz , Vivek De , Shekhar Borkar
IPC分类号： H01L23/02
CPC分类号： H01L25/18 , H01L2224/05001 , H01L2224/05026 , H01L2224/0557 , H01L2224/05571 , H01L2224/13025 , H01L2224/16145 , H01L2224/16225 , H01L2225/06513 , H01L2225/06541 , H01L2225/06565 , H01L2924/00014 , H01L2924/1305 , H01L2924/13091 , H01L2924/15311 , H01L2924/00 , H01L2224/05005 , H01L2224/05541 , H01L2224/05599
摘要： Apparatus, system and method for managing power of a main circuitry disposed on a main substrate using a control circuitry disposed on a control substrate, in a stacked relationship with the main substrate, are described herein.
摘要翻译：这里描述了使用设置在控制基板上的与主基板堆叠关系的设置在主基板上的主电路的电力的装置，系统和方法。

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