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131. 发明授权

US07361026B2 Land grid array (LGA) interposer utilizing metal-on-elastomer hemi-torus and other multiple points of contact geometries 有权
公开(公告)号：US07361026B2
公开(公告)日：2008-04-22
申请号：US11865440
申请日：2007-10-01
申请人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
发明人： Gareth G. Hougham , Brian S. Beaman , Evan G. Colgan , Paul W. Coteus , Stefano S. Oggioni , Enrique Vargas
IPC分类号： H01R12/00
CPC分类号： H01R12/714 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01R12/52 , H05K3/326 , H05K3/4007 , H05K7/1061 , H05K2201/0133 , H05K2201/0367 , H05K2201/09481 , H05K2201/09745 , H05K2201/10378 , H05K2201/10734 , Y10T29/49002 , Y10T29/49121 , Y10T29/49124 , Y10T29/49126 , Y10T29/49128 , Y10T29/4913 , Y10T29/49147 , Y10T29/49149 , Y10T29/49151 , Y10T29/49155 , Y10T29/49158 , Y10T29/49165 , Y10T29/49204 , Y10T29/49208 , Y10T29/49213 , Y10T29/49218 , Y10T29/49222 , H01L2924/00
摘要： A land grid array (LGA) interposer structure, including an electrically insulating carrier plane, and at least one interposer mounted on a first surface of said carrier plane. The interposer possesses a hemi-toroidal configuration in transverse cross-section and is constituted of a dielectric elastomeric material. A plurality of electrically-conductive elements are arranged about the surface of the at least one hemi-toroidal interposer and extend radically inwardly and downwardly from an uppermost end thereof into electrical contact with at least one component located on an opposite side of the electrically insulating carrier plane. Provided is also a method of producing the land grid array interposer structure.

132. 发明申请

US20080054430A1 Through board stacking of multiple LGA-connected components 有权
标题翻译：通过板堆叠多个LGA连接的组件
公开(公告)号：US20080054430A1
公开(公告)日：2008-03-06
申请号：US11511815
申请日：2006-08-29
申请人： Paul W. Coteus , Shawn A. Hall , Gareth G. Hougham , Alphonso P. Lanzetta , Rick A. Rand
发明人： Paul W. Coteus , Shawn A. Hall , Gareth G. Hougham , Alphonso P. Lanzetta , Rick A. Rand
IPC分类号： H01L23/02
CPC分类号： H05K3/325 , H05K2201/0314 , H05K2201/10545 , H05K2201/10719 , H05K2201/2018
摘要： A package design is provided where a chip module is connected to a printed circuit board (PCB) via a land grid array (LGA) on the top surface of the PCB, and where a power supply is connected to the PCB via a second LGA on the bottom surface of the PCB. The stack of the chip module, power supply, and LGA is held in place and compressed with actuation hardware forming an adjustable frame. The package allows field replacibility of either the module, or the PS, and provides the shortest possible wiring distance from the PS to the module leading to higher performance.
摘要翻译：提供了一种封装设计，其中芯片模块通过PCB顶表面上的焊盘网格阵列（LGA）连接到印刷电路板（PCB），并且电源通过第二个LGA连接到PCB PCB的底面。芯片模块，电源和LGA的堆叠被保持就位并用致动硬件压缩形成可调节的框架。该封装允许模块或PS的现场可替代性，并提供从PS到模块的最短可能布线距离，从而实现更高的性能。

133. 发明授权

US07305487B2 Optimized scalable network switch 失效
标题翻译：优化可扩展网络交换机
公开(公告)号：US07305487B2
公开(公告)日：2007-12-04
申请号：US10469001
申请日：2002-02-25
申请人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Paul W. Coteus , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Burkhard D. Steinmacher-Burow , Todd E. Takken , Pavlos M. Vranas
IPC分类号： G06F15/173
CPC分类号： H05K7/20836 , F24F11/77 , G06F9/52 , G06F9/526 , G06F15/17381 , G06F17/142 , G09G5/008 , H04L7/0338
摘要： In a massively parallel computing system having a plurality of nodes configured in m multi-dimensions, each node including a computing device, a method for routing packets towards their destination nodes is provided which includes generating at least one of a 2m plurality of compact bit vectors containing information derived from downstream nodes. A multilevel arbitration process in which downstream information stored in the compact vectors, such as link status information and fullness of downstream buffers, is used to determine a preferred direction and virtual channel for packet transmission. Preferred direction ranges are encoded and virtual channels are selected by examining the plurality of compact bit vectors. This dynamic routing method eliminates the necessity of routing tables, thus enhancing scalability of the switch.
摘要翻译：在具有以m多维配置的多个节点的大规模并行计算系统中，每个节点包括计算设备，提供了用于向分组朝向其目的地节点路由分组的方法，其包括生成2m个多个紧凑比特向量中的至少一个包含从下游节点导出的信息。存储在紧凑向量中的下行信息（诸如链路状态信息和下游缓冲器的丰满度）的多级仲裁过程被用于确定分组传输的优选方向和虚拟信道。优选的方向范围被编码，并且通过检查多个紧凑比特向量来选择虚拟信道。这种动态路由方法消除了路由表的必要性，从而增强了交换机的可扩展性。

134. 发明授权

US07210088B2 Fault isolation through no-overhead link level CRC 失效
标题翻译：通过无架空链路级CRC进行故障隔离
公开(公告)号：US07210088B2
公开(公告)日：2007-04-24
申请号：US10468996
申请日：2002-02-25
申请人： Dong Chen , Paul W. Coteus , Alan G. Gara
发明人： Dong Chen , Paul W. Coteus , Alan G. Gara
IPC分类号： G06F11/00 , G06F13/00 , G06F7/02 , H03M13/00
CPC分类号： H03M13/091 , G11B20/1833 , H04L1/0061
摘要： A fault isolation technique for checking the accuracy of data packets transmitted between nodes of a parallel processor. An independent crc is kept of all data sent from one processor to another, and received from one processor to another. At the end of each checkpoint, the crcs are compared. If they do not match, there was an error. The crcs may be cleared and restarted at each checkpoint. In the preferred embodiment, the basic functionality is to calculate a CRC of all packet data that has been successfully transmitted across a given link. This CRC is done on both ends of the link, thereby allowing an independent check on all data believed to have been correctly transmitted. Preferably, all links have this CRC coverage, and the CRC used in this link level check is different from that used in the packet transfer protocol. This independent check, if successfully passed, virtually eliminates the possibility that any data errors were missed during the previous transfer period.
摘要翻译：用于检查并行处理器节点之间传输的数据包的精度的故障隔离技术。保持从一个处理器发送到另一个处理器的所有数据的独立crc，并从一个处理器接收另一个处理器。在每个检查点的末尾，比较crcs。如果它们不匹配，则出现错误。可以在每个检查点清除并重新启动crcs。在优选实施例中，基本功能是计算已经通过给定链路成功发送的所有分组数据的CRC。该CRC在链路的两端完成，从而允许对所有被认为已被正确发送的数据进行独立的检查。优选地，所有链路具有该CRC覆盖，并且在该链路级检查中使用的CRC与在分组传送协议中使用的不同。这种独立检查，如果成功通过，几乎消除了在以前的传输期间错过任何数据错误的可能性。

135. 发明授权

US06807125B2 Circuit and method for reading data transfers that are sent with a source synchronous clock signal 失效
标题翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法
公开(公告)号：US06807125B2
公开(公告)日：2004-10-19
申请号：US10225871
申请日：2002-08-22
申请人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
发明人： Paul W. Coteus , Frank D. Ferraiolo , Kevin C. Gower
IPC分类号： G11C1100
CPC分类号： G11C7/106 , G11C7/1045 , G11C7/1051 , G11C7/1066
摘要： A circuit and method for reading data transfers that are sent with a source synchronous clock signal. The circuit has a data input for receiving data signals carrying data being transferred, a clock input for receiving synchronous clock signals, and a delay circuit connected to the clock input for generating a delayed clock signal which is delayed from said synchronous clock signal a predetermined time period. The circuit also includes a pipeline connected to the data input for sampling the data on the data input in response to said delayed clock signal thereby stretching the sampling of incoming data.
摘要翻译：用于读取与源同步时钟信号一起发送的数据传输的电路和方法。该电路具有数据输入端，用于接收承载传送数据的数据信号，用于接收同步时钟信号的时钟输入端和连接到时钟输入端的延迟电路，用于产生从所述同步时钟信号延迟预定时间的延迟时钟信号期。电路还包括连接到数据输入端的流水线，用于响应于所述延迟的时钟信号对数据输入上的数据进行采样，从而延伸输入数据的采样。

136. 发明授权

US06178126B1 Memory and system configuration for programming a redundancy address in an electric system 有权
标题翻译：用于编程电气系统中冗余地址的存储器和系统配置
公开(公告)号：US06178126B1
公开(公告)日：2001-01-23
申请号：US09534423
申请日：2000-03-23
申请人： Toshiaki Kirihata , Paul W. Coteus , Warren E. Maule , Steven Tomashot
发明人： Toshiaki Kirihata , Paul W. Coteus , Warren E. Maule , Steven Tomashot
IPC分类号： G11C1300
CPC分类号： G11C29/72 , G11C29/785
摘要： A redundancy address in a plurality of memory devices is identified by at least two protocols available in an electric system. The first protocol is a mode register set command (or extended mode register set command). A chip select signal determines one of a plurality of memory modules, where a memory device is identified with at least one data port. Alternatively, a data strobe port or a data mask port may be preferably used for the selection of the memory devices instead of using the data port. The second protocol is a RAM access command which identifies a defective memory cell address (redundancy address) within the selected RAM by way of a plurality of address ports (ADRs). A redundancy address programming method is realized by way of electrically programmable fuses or by dynamically programmable redundancy latches integrated in each memory. The electric system configuration preferably includes a non-volatile storage device for storing a data port organization for the memory devices. Therein, the relation between the system memory data bus and the memory data ports for the memory devices are recognized by a memory controller. A microprocessor in the electric system is used for testing the memories and for analyzing the redundancy address. The present invention further includes a post device identification protocol to effectively debug field problems.
摘要翻译：多个存储设备中的冗余地址由电气系统中可用的至少两种协议来识别。第一个协议是模式寄存器设置命令（或扩展模式寄存器设置命令）。芯片选择信号确定多个存储器模块中的一个，其中存储器件被识别为具有至少一个数据端口。或者，可以优选地使用数据选通端口或数据掩码端口来选择存储设备，而不是使用数据端口。第二协议是RAM访问命令，其通过多个地址端口（ADR）识别所选择的RAM内的有缺陷的存储器单元地址（冗余地址）。通过电可编程熔丝或集成在每个存储器中的动态可编程冗余锁存器实现冗余地址编程方法。电气系统配置优选地包括用于存储用于存储器件的数据端口组织的非易失性存储设备。其中，存储器控制器识别系统存储器数据总线与存储器件的存储器数据端口之间的关系。电气系统中的微处理器用于测试存储器和分析冗余地址。本发明还包括有效调试现场问题的后期设备识别协议。

137. 发明授权

US5614920A Secure viewing of display units using an electronic shutter 失效
标题翻译：使用电子快门查看显示单元
公开(公告)号：US5614920A
公开(公告)日：1997-03-25
申请号：US342953
申请日：1994-11-21
申请人： Paul W. Coteus , Douglas S. Goodman
发明人： Paul W. Coteus , Douglas S. Goodman
IPC分类号： G06F1/00 , G06F21/00 , G09G5/00
CPC分类号： G06F21/84 , H04N13/0438 , H04N2013/0463
摘要： Apparatus for masking a displayed image by merging it with a second featureless image made of short pulses of light that are introduced into a transparent screen disposed between the display and the viewer. An electronic shutter timed to match the sequence of the masking light pulses separates or blocks the masking image to permit the primary image to be viewed only by the person having the electronic shutter.
摘要翻译：用于通过将显示图像与由引导到布置在显示器和观看者之间的透明屏幕的短脉冲光构成的第二无特征图像进行合并来掩蔽所显示的图像的装置。定时匹配屏蔽光脉冲序列的电子快门分离或阻挡掩蔽图像，以允许仅由具有电子快门的人观看主图像。

138. 发明授权

US5480841A Process of multilayer conductor chip packaging 失效
标题翻译：多层导体芯片封装工艺
公开(公告)号：US5480841A
公开(公告)日：1996-01-02
申请号：US302084
申请日：1994-09-07
申请人： Harry R. Bickford , Paul W. Coteus , Linda C. Matthew
发明人： Harry R. Bickford , Paul W. Coteus , Linda C. Matthew
IPC分类号： H01L23/02 , H01L23/10 , H01L23/495 , H01L23/498 , H01L23/50 , H05K3/34 , H01L21/60
CPC分类号： H05K3/3426 , H01L23/4951 , H01L23/49534 , H01L23/49572 , H01L23/49822 , H01L23/50 , H01L24/48 , H01L2224/05554 , H01L2224/05599 , H01L2224/45015 , H01L2224/48091 , H01L2224/48095 , H01L2224/4824 , H01L2224/4826 , H01L2224/48464 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/181 , H01L2924/20751 , H01L2924/20752 , H01L2924/3011 , H01L2924/351 , H05K2201/10568 , H05K2201/10681 , H05K2201/10689 , Y02P70/613
摘要： A process of providing an external wiring and connecting package for a semiconductor chip wherein the chip is a major contributor to the strength of the package. External contacts and wiring are provided by a multilayer wiring member that may include a mesh ground plane with embedded power bus layer over a conductor layer for expansion mismatch control and impedance control, a protective encapsulation covers the bonds from the wiring conductors to the chip, and external contact connections employ fused metal through the contact members.
摘要翻译：提供用于半导体芯片的外部布线和连接封装的工艺，其中芯片是封装强度的主要贡献者。外部触点和布线由多层布线构件提供，多层布线构件可以包括在导体层上的嵌入式电源总线层的网格接地面，用于扩展失配控制和阻抗控制，保护封装覆盖从布线导体到芯片的接合，以及外部接触连接通过接触构件使用熔融金属。

139. 发明授权

US09272498B2 Precast thermal interface adhesive for easy and repeated, separation and remating 有权
标题翻译：预制热界面粘合剂，易于重复，分离和重新配制
公开(公告)号：US09272498B2
公开(公告)日：2016-03-01
申请号：US13546151
申请日：2012-07-11
申请人： Evan George Colgan , Paul W. Coteus , Michael Anthony Gaynes , Kenneth Charles Marston , Steven P. Ostrander
发明人： Evan George Colgan , Paul W. Coteus , Michael Anthony Gaynes , Kenneth Charles Marston , Steven P. Ostrander
IPC分类号： B32B15/08 , B32B37/12 , B32B37/26 , B32B37/24
CPC分类号： B32B37/1207 , B32B37/26 , B32B2037/243 , B32B2037/268 , B32B2309/02 , B32B2311/12 , B32B2311/24 , B32B2457/08 , Y10T156/11 , Y10T156/1195 , Y10T428/2804 , Y10T428/2813 , Y10T428/2861
摘要： Precast curable thermal interface adhesives facilitating the easy and repeatable separation and remaining of electronic components at thermal interfaces thereof, and a method for implementing the foregoing repeatable separation and remating at the thermal interfaces of components through the use of such adhesives.
摘要翻译：预制的可固化热界面粘合剂便于在其热界面处容易且可重复地分离和保留电子部件，以及用于通过使用这种粘合剂在组件的热界面处实现上述可重复分离和重新化的方法。

140. 发明授权

US09037892B2 System-wide power management control via clock distribution network 有权
标题翻译：通过时钟分配网络进行全系统的电源管理控制
公开(公告)号：US09037892B2
公开(公告)日：2015-05-19
申请号：US13085879
申请日：2011-04-13
申请人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
发明人： Paul W. Coteus , Alan Gara , Thomas M. Gooding , Rudolf A. Haring , Gerard V. Kopcsay , Thomas A. Liebsch , Don D. Reed
IPC分类号： G06F1/04 , G06F1/12 , G06F1/32 , G06F1/10 , G06F1/20
CPC分类号： G06F1/329 , G06F1/10 , G06F1/12 , G06F1/206 , G06F1/3206 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/16 , Y02D10/172 , Y02D10/24
摘要： An apparatus, method and computer program product for automatically controlling power dissipation of a parallel computing system that includes a plurality of processors. A computing device issues a command to the parallel computing system. A clock pulse-width modulator encodes the command in a system clock signal to be distributed to the plurality of processors. The plurality of processors in the parallel computing system receive the system clock signal including the encoded command, and adjusts power dissipation according to the encoded command.
摘要翻译：一种用于自动控制包括多个处理器的并行计算系统的功耗的装置，方法和计算机程序产品。计算设备向并行计算系统发出命令。时钟脉冲宽度调制器对系统时钟信号中的命令进行编码，以分配给多个处理器。并行计算系统中的多个处理器接收包括编码命令的系统时钟信号，并根据编码命令调整功耗。

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