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131. 发明申请

US20090215238A1 METHODS OF FABRICATING SEMICONDUCTOR DEVICES WITH ENLARGED RECESSED GATE ELECTRODES 有权
标题翻译：制造具有扩展的门控电极的半导体器件的方法
公开(公告)号：US20090215238A1
公开(公告)日：2009-08-27
申请号：US12431488
申请日：2009-04-28
申请人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
发明人： Seong-Ho Kim , Chang-Sub Lee , Jeong-Dong Choe , Sung-Min Kim , Shin-Ae Lee , Dong-Gun Park
IPC分类号： H01L21/336
CPC分类号： H01L29/4983 , H01L21/28114 , H01L29/42376 , H01L29/665 , H01L29/66553 , H01L29/6656 , H01L29/6659 , H01L29/66621 , H01L29/7833 , H01L29/7834
摘要： A semiconductor device includes a semiconductor substrate having a recess therein. A gate insulator is disposed on the substrate in the recess. The device further includes a gate electrode including a first portion on the gate insulator in the recess and a second reduced-width portion extending from the first portion. A source/drain region is disposed in the substrate adjacent the recess. The recess may have a curved shape, e.g., may have hemispherical or ellipsoid shape. The source/drain region may include a lighter-doped portion adjoining the recess. Relate fabrication methods are also discussed.
摘要翻译：半导体器件包括其中具有凹部的半导体衬底。栅极绝缘体设置在凹部中的基板上。该器件还包括栅电极，其包括位于凹槽中的栅极绝缘体上的第一部分和从第一部分延伸的第二缩小宽度部分。源极/漏极区域设置在邻近凹部的衬底中。凹部可以具有弯曲的形状，例如可以具有半球形或椭球形。源极/漏极区域可以包括邻近凹部的较轻掺杂部分。还讨论了相关制造方法。

132. 发明授权

US07566929B2 Nonvolatile memory devices having floating gate electrodes with nitrogen-doped layers on portions thereof 有权
标题翻译：具有在其部分上具有氮掺杂层的浮置栅电极的非易失性存储器件
公开(公告)号：US07566929B2
公开(公告)日：2009-07-28
申请号：US11471798
申请日：2006-06-21
申请人： Chang-Hyun Lee , Dong-Gun Park
发明人： Chang-Hyun Lee , Dong-Gun Park
IPC分类号： H01L29/788
CPC分类号： H01L21/265 , B82Y10/00 , H01L21/28202 , H01L21/28273 , H01L21/28282 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42324 , H01L29/513 , H01L29/66825 , H01L29/66833 , H01L29/7881 , H01L29/7885 , H01L29/792
摘要： Nonvolatile memory devices are provided including an integrated circuit substrate and a charge storage pattern on the integrated circuit substrate. The charge storage pattern has a sidewall and a tunnel insulating layer is provided between the charge storage pattern and the integrated circuit substrate. A gate pattern is provided on the charge storage pattern. A blocking insulating layer is provided between the charge storage pattern and the gate pattern. The sidewall of the charge storage pattern includes a first nitrogen doped layer. Related methods of fabricating nonvolatile memory devices are also provided herein.
摘要翻译：在集成电路基板上提供集成电路基板和电荷存储图案的非易失性存储器件。电荷存储图案具有侧壁，并且在电荷存储图案和集成电路基板之间设置隧道绝缘层。在电荷存储图案上提供栅极图案。在电荷存储图案和栅极图案之间设置隔离绝缘层。电荷存储图案的侧壁包括第一氮掺杂层。本文还提供了制造非易失性存储器件的相关方法。

133. 发明授权

US07521766B2 Transistor and method of forming the same 有权
标题翻译：晶体管及其形成方法
公开(公告)号：US07521766B2
公开(公告)日：2009-04-21
申请号：US11070598
申请日：2005-03-01
申请人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
发明人： Jae-Man Yoon , Choong-Ho Lee , Dong-Gun Park , Chul Lee
IPC分类号： H01L27/088
CPC分类号： H01L29/785 , H01L29/66795
摘要： According to some embodiments of the invention, a fin type transistor includes an active structure integrally formed with a silicon substrate. The active structure includes grooves that form blocking regions under source/drain regions. A gate structure is formed to cross the upper face of the active structure and to cover the exposed side surfaces of the lateral portions of the active structure. An effective channel length of a fin type transistor may be sufficiently ensured so that a short channel effect of the transistor may be prevented and the fin type transistor may have a high breakdown voltage.
摘要翻译：根据本发明的一些实施例，鳍型晶体管包括与硅衬底一体形成的有源结构。活性结构包括在源极/漏极区域下形成阻挡区的沟槽。栅极结构形成为跨越有源结构的上表面并且覆盖有源结构的侧部的暴露的侧表面。可以充分确保翅片型晶体管的有效沟道长度，从而可以防止晶体管的短沟道效应，并且鳍式晶体管可能具有高击穿电压。

134. 发明授权

US07419859B2 Method of fabricating a semiconductor device having a single gate electrode corresponding to a pair of fin-type channel regions 有权
标题翻译：制造具有对应于一对鳍型沟道区的单个栅电极的半导体器件的方法
公开(公告)号：US07419859B2
公开(公告)日：2008-09-02
申请号：US11505335
申请日：2006-08-17
申请人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
发明人： Suk-Pil Kim , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Eun-Suk Cho , Suk-Kang Sung , Byung-Yong Choi , Tae-Yong Kim , Choong-Ho Lee
IPC分类号： H01L21/84 , H01L29/94
CPC分类号： H01L29/785 , H01L21/28273 , H01L21/28282 , H01L21/84 , H01L27/10873 , H01L27/10879 , H01L27/1159 , H01L27/2436 , H01L29/66795
摘要： Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.
摘要翻译：提供了制造具有提供体偏置控制的鳍式FET结构的半导体器件的方法，显示出与SOI结构相关的一些特征优点，提供增加的工作电流和/或降低的接触电阻。制造半导体器件的方法包括在第一绝缘膜的突出部分的侧壁上形成绝缘间隔物; 通过使用绝缘间隔物作为蚀刻掩模去除半导体衬底的暴露区域，从而形成与第一绝缘膜接触并由第一绝缘膜支撑的鳍形成第二沟槽。在形成翅片之后，形成第三绝缘膜以填充第二沟槽并支撑翅片。然后去除第一绝缘膜的一部分以打开翅片之间的空间，其中可以形成包括栅极电介质，栅电极和附加接触，绝缘和存储节点结构的附加结构。

135. 发明申请

US20080194065A1 INTEGRATED CIRCUIT DEVICES HAVING AN EPITAXIAL PATTERN WITH A VOID REGION FORMED THEREIN AND METHODS OF FORMING THE SAME 审中-公开
标题翻译：具有形成有空位区域的外延图案的集成电路装置及其形成方法
公开(公告)号：US20080194065A1
公开(公告)日：2008-08-14
申请号：US12107468
申请日：2008-04-22
申请人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
发明人： Sung-Young Lee , Sung-Min Kim , Dong-Gun Park , Kyoung-Hwan Yeo
IPC分类号： H01L21/02
CPC分类号： H01L29/66651 , H01L21/76224 , H01L21/76289 , H01L21/764 , H01L29/0649 , H01L29/66795 , H01L29/785 , H01L29/78603 , H01L29/802
摘要： An integrated circuit device includes a substrate. An epitaxial pattern is on the substrate and has a pair of impurity diffusion regions formed therein and a pair of void regions formed therein that are disposed between the pair of impurity diffusion regions and the substrate. Respective ones of the pair of impurity diffusion regions at least partially overlap respective ones of the pair of void regions. A gate electrode is on the epitaxial pattern between respective ones of the pair of impurity diffusion regions.
摘要翻译：集成电路器件包括衬底。外延图案位于基板上，并且在其间形成有一对杂质扩散区域和形成在其中的一对空隙区域，其设置在该对杂质扩散区域和基板之间。该对杂质扩散区域中的各一个至少部分地重叠该对空隙区域中的相应的一个。栅极电极位于一对杂质扩散区域中的各自之间的外延图案上。

136. 发明授权

US07407845B2 Field effect transistor and method for manufacturing the same 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US07407845B2
公开(公告)日：2008-08-05
申请号：US11048369
申请日：2005-01-31
申请人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
发明人： Choong-Ho Lee , Jae-Man Yoon , Dong-Gun Park , Chul Lee
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/785 , H01L29/7854 , H01L29/78603 , H01L29/78648
摘要： In one embodiment, a semiconductor device includes a semiconductor substrate having a lower layer and an upper layer overlying the lower layer. The upper layer is arranged and structured to form first and second active regions that are spaced apart from each other and protrude from an upper surface of the lower layer. A third active region of a bridge shape is distanced vertically from the upper surface of the lower layer and connects the first and second active regions. The device further includes a gate electrode, which is formed with a gate insulation layer surrounding the third active region, so that the third active region functions as a channel.
摘要翻译：在一个实施例中，半导体器件包括具有下层和覆盖在下层上的上层的半导体衬底。上层被布置和构造成形成彼此间隔开并从下层的上表面突出的第一和第二有源区。桥接形状的第三有源区域与下层的上表面垂直地间隔开并且连接第一和第二有源区域。该器件还包括栅电极，其形成有围绕第三有源区的栅绝缘层，使得第三有源区用作沟道。

137. 发明授权

US07381601B2 Methods of fabricating field effect transistors having multiple stacked channels 有权
标题翻译：制造具有多个堆叠通道的场效应晶体管的方法
公开(公告)号：US07381601B2
公开(公告)日：2008-06-03
申请号：US10841870
申请日：2004-05-07
申请人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
发明人： Sung-Min Kim , Dong-Gun Park , Chang-Sub Lee , Jeong-Dong Choe , Shin-Ae Lee , Seong-Ho Kim
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L29/785 , H01L21/823412 , H01L29/42356 , H01L29/42384 , H01L29/42392 , H01L29/66477 , H01L29/66545 , H01L29/66636 , H01L29/66772 , H01L29/66787 , H01L29/78 , H01L29/78642 , H01L29/78654 , H01L29/78696
摘要： Integrated circuit field effect transistor devices include a substrate having a surface and an active channel pattern on the surface. The active channel pattern includes channels that are stacked upon one another and are spaced apart from one another to define at least one tunnel between adjacent channels. A gate electrode surrounds the channels and extends through the at least one tunnel. A pair of source/drain regions also is provided. Integrated circuit field effect transistors are manufactured, by forming a pre-active pattern on a surface of a substrate. The pre-active pattern includes a series of interchannel layers and channel layers stacked alternately upon each other. Source/drain regions are formed on the substrate at opposite ends of the pre-active pattern. The interchannel layers are selectively removed to form tunnels. A gate electrode is formed in the tunnels and surrounding the channels.
摘要翻译：集成电路场效应晶体管器件包括在表面上具有表面和有源沟道图案的衬底。活动通道图案包括彼此堆叠并且彼此间隔开以限定相邻通道之间的至少一个通道的通道。栅电极围绕通道并延伸穿过至少一个通道。还提供了一对源极/漏极区域。通过在衬底的表面上形成预活性图案来制造集成电路场效应晶体管。预激活图案包括彼此交替堆叠的一系列通道间层和沟道层。源极/漏极区域在预活化图案的相对端处在衬底上形成。选择性地去除通道间层以形成隧道。在隧道中形成栅电极并围绕通道。

138. 发明授权

US07317230B2 Fin FET structure 有权
标题翻译：翅片FET结构
公开(公告)号：US07317230B2
公开(公告)日：2008-01-08
申请号：US11041063
申请日：2005-01-21
申请人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
发明人： Choong-Ho Lee , Dong-Gun Park , Jae-Man Youn , Chul Lee
IPC分类号： H01L29/94
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795 , H01L29/7854
摘要： A fin FET structure employs a negative word line scheme. A gate electrode of a fin FET employs an electrode doped with n+ impurity, and a channel doping for a control of threshold voltage is not executed, or the channel doping is executed by a low density, thereby remarkably improving characteristics of the fin FET. A semiconductor substrate is formed in a first conductive type, and a fin active region of a first conductive type is projected from an upper surface of the semiconductor substrate and is connected to the semiconductor substrate. An insulation layer is formed on the semiconductor substrate, and a gate insulation layer is formed in upper part and sidewall of the fin active region. A gate electrode is formed on the insulation layer and the gate insulation layer. Source and drain are formed in the fin active region of both sides of the gate electrode.
摘要翻译：鳍式FET结构采用负字线方案。翅片FET的栅极采用掺杂有n +杂质的电极，不执行用于阈值电压控制的沟道掺杂，或者通过低密度执行沟道掺杂，从而显着提高了鳍式FET的特性。半导体衬底形成为第一导电类型，并且第一导电类型的鳍有源区域从半导体衬底的上表面突出并连接到半导体衬底。在半导体衬底上形成绝缘层，并且在翅片有源区的上部和侧壁形成栅极绝缘层。在绝缘层和栅极绝缘层上形成栅电极。源极和漏极形成在栅极两侧的鳍片有源区域中。

139. 发明申请

US20070145431A1 Fin-FET having GAA structure and methods of fabricating the same 有权
标题翻译：具有GAA结构的Fin-FET及其制造方法
公开(公告)号：US20070145431A1
公开(公告)日：2007-06-28
申请号：US11505936
申请日：2006-08-18
申请人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
发明人： Suk-Pil Kim , Jae-Woong Hyun , Yoon-Dong Park , Won-Joo Kim , Dong-Gun Park , Choong-Ho Lee
IPC分类号： H01L29/76
CPC分类号： H01L29/785 , H01L29/42392 , H01L29/66795
摘要： Example embodiments of the present invention relate to a semiconductor device and methods of fabricating the same. Other example embodiments of the present invention relate to a fin-field effect transistor (Fin-FET) having a fin-type channel region and methods of fabricating the same. A Fin-FET having a gate all around (GAA) structure that may use an entire area around a fin as a channel region is provided. The Fin-FET having the GAA structure includes a semiconductor substrate having a body, a pair of support pillars and a fin. The pair of support pillars may protrude from the body. A fin may be spaced apart from the body and may have ends connected to and supported by the pair of support pillars. A gate electrode may surround at least a portion of the fin of the semiconductor substrate. The gate electrode may be insulated from the semiconductor substrate. A gate insulation layer may be interposed between the gate electrode and the fin of the semiconductor substrate.
摘要翻译：本发明的示例性实施例涉及一种半导体器件及其制造方法。本发明的其它示例性实施例涉及一种具有鳍型沟道区的鳍式场效应晶体管（Fin-FET）及其制造方法。提供了可以使用围绕鳍片的整个区域作为沟道区域的具有栅极全（GAA）结构的鳍FET。具有GAA结构的Fin-FET包括具有主体，一对支撑柱和鳍的半导体衬底。一对支柱可能从身体突出。翅片可以与主体间隔开，并且可以具有连接到一对支撑柱并由其支撑的端部。栅电极可围绕半导体衬底的鳍的至少一部分。栅电极可以与半导体衬底绝缘。栅极绝缘层可以插入在半导体衬底的栅电极和鳍之间。

140. 发明申请

US20070080385A1 Semiconductor device having vertical transistor and method of fabricating the same 有权
标题翻译：具有垂直晶体管的半导体器件及其制造方法
公开(公告)号：US20070080385A1
公开(公告)日：2007-04-12
申请号：US11450936
申请日：2006-06-09
申请人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
发明人： Bong-Soo Kim , Kang-Yoon Lee , Dong-Gun Park , Jae-Man Yoon , Seong-Goo Kim , Hyeoung-Won Seo
IPC分类号： H01L29/94
CPC分类号： H01L27/10894 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures. A bit line separation insulating layer and a peripheral circuit isolation layer are formed inside the bit line separation trench and the peripheral circuit trench, respectively.
摘要翻译：提供了具有垂直晶体管的半导体器件及其制造方法。该方法包括制备具有单元区域和外围电路区域的半导体衬底。在单元区域的基板上形成沿行方向和列方向二维排列的岛状的垂直栅极结构。每个垂直栅极结构包括半导体柱和围绕半导体柱的中心部分的栅电极。在垂直栅极结构之间的间隙区域的下方，在半导体衬底的内部形成有位线分离沟槽，并且在外围电路区域的半导体衬底的内部形成限制外围电路有源区的外围电路沟道。位线分离沟槽与垂直栅极结构的列方向平行地形成。位线分离绝缘层和外围电路隔离层分别形成在位线分离沟槽和外围电路沟槽内部。

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