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131. 发明授权

US07229909B2 Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes 失效
标题翻译：集成电路芯片利用由碳纳米管形成的具有取向的圆柱形空隙的电介质层
公开(公告)号：US07229909B2
公开(公告)日：2007-06-12
申请号：US11008800
申请日：2004-12-09
申请人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark Charles Hakey , Steven John Holmes , David Vaclav Horak , Charles William Koburger, III , Peter H. Mitchell
IPC分类号： H01L21/00
CPC分类号： B82Y10/00 , H01L21/7682 , H01L23/5222 , H01L23/53238 , H01L23/5329 , H01L2924/0002 , Y10S977/742 , Y10S977/842 , H01L2924/00
摘要： A dielectric in an integrated circuit is formed by creating oriented cylindrical voids in a conventional dielectric material. Preferably, voids are formed by first forming multiple relatively long, thin carbon nanotubes perpendicular to a surface of an integrated circuit wafer, by depositing a conventional dielectric on the surface to fill the area between the carbon nanotubes, and by then removing the carbon nanotubes to produce voids in place of the carbon nanotubes. A layer of dielectric and voids thus formed can be patterned or otherwise processed using any of various conventional processes. The use of a conventional dielectric material having numerous air voids substantially reduces the dielectric constant, leaving a dielectric structure which is both structurally strong and can be constructed compatibly with conventional processes and materials.
摘要翻译：集成电路中的电介质通过在常规电介质材料中产生取向的圆柱形空隙来形成。优选地，通过首先通过在表面上沉积常规电介质以填充碳纳米管之间的区域，然后通过将碳纳米管去除以形成多个相对较长的薄碳纳米管，形成集成电路晶片的表面，形成空隙产生代替碳纳米管的空隙。由此形成的电介质层和空隙层可以使用各种常规方法中的任一种进行图案化或以其他方式处理。使用具有多个空气空隙的常规电介质材料基本上降低了介电常数，留下了在结构上很强并且可以与常规工艺和材料相容地构造的电介质结构。

132. 发明授权

US07229889B2 Methods for metal plating of gate conductors and semiconductors formed thereby 有权
标题翻译：由此形成的栅极导体和半导体的金属电镀方法
公开(公告)号：US07229889B2
公开(公告)日：2007-06-12
申请号：US10906881
申请日：2005-03-10
申请人： Steven J. Holmes , Charles W. Koburger, III , David V. Horak , Toshiharu Furukawa , Mark C. Hakey
发明人： Steven J. Holmes , Charles W. Koburger, III , David V. Horak , Toshiharu Furukawa , Mark C. Hakey
IPC分类号： H01L21/20
CPC分类号： H01L29/785 , H01L29/4908 , H01L29/66795
摘要： A method of metal plating a gate conductor on a semiconductor is provided. The method includes defining an organic polymer plating mandrel on the semiconductor, activating one or more sites of the organic polymer plating mandrel, and binding a seed layer to the one or more of the activated sites. A metallic conductive material can then be plated on the seed layer to form the gate conductor. Semiconductor devices having a gate conductor plated thereon to a width of between about 1 to about 7 nanometers are also provided.
摘要翻译：提供了一种对半导体上的栅极导体进行金属镀覆的方法。该方法包括在半导体上限定有机聚合物电镀心轴，激活有机聚合物电镀心轴的一个或多个位点，以及将种子层结合到一个或多个活化位点。然后可以将金属导电材料电镀在种子层上以形成栅极导体。还提供了其上镀有宽度在约1至约7纳米之间的栅极导体的半导体器件。

133. 发明申请

US20070125946A1 Y-SHAPED CARBON NANOTUBES AS AFM PROBE FOR ANALYZING SUBSTRATES WITH ANGLED TOPOGRAPHY 有权
标题翻译： Y型碳纳米管作为AFM探针，用于分析具有光滑地理位置的基底
公开(公告)号：US20070125946A1
公开(公告)日：2007-06-07
申请号：US11164792
申请日：2005-12-06
申请人： Carol Boye , Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Carol Boye , Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： G21K7/00
CPC分类号： G01Q60/42 , G01Q70/12
摘要： A Y-shaped carbon nanotube atomic force microscope probe tip and methods comprise a shaft portion; a pair of angled arms extending from a same end of the shaft portion, wherein the shaft portion and the pair of angled arms comprise a chemically modified carbon nanotube, and wherein the chemically modified carbon nanotube is modified with any of an amine, carboxyl, fluorine, and metallic component. Preferably, each of the pair of angled arms comprises a length of at least 200 nm and a diameter between 10 and 200 nm. Moreover, the chemically modified carbon nanotube is preferably adapted to allow differentiation between substrate materials to be probed. Additionally, the chemically modified carbon nanotube is preferably adapted to allow fluorine gas to flow through the chemically modified carbon nanotube onto a substrate to be characterized. Furthermore, the chemically modified carbon nanotube is preferably adapted to chemically react with a substrate surface to be characterized.
摘要翻译： Y型碳纳米管原子力显微镜探针头和方法包括轴部分; 一对成角度的臂，其从所述轴部的同一端延伸，其中所述轴部和所述一对成角度的臂包括化学改性的碳纳米管，并且其中所述化学改性的碳纳米管用胺，羧基，氟，和金属成分。优选地，一对成角度的臂中的每一个包括至少200nm的长度和10和200nm之间的直径。此外，化学改性的碳纳米管优选适于允许待探测的基底材料之间的分化。此外，化学改性的碳纳米管优选适于使氟气通过化学改性的碳纳米管流动到待表征的基底上。此外，化学改性的碳纳米管优选适于与要表征的基材表面发生化学反应。

134. 发明申请

US20070108473A1 SEMICONDUCTOR OPTICAL SENSORS 有权
标题翻译：半导体光传感器
公开(公告)号：US20070108473A1
公开(公告)日：2007-05-17
申请号：US11164217
申请日：2005-11-15
申请人： Toshiharu Furukawa , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L29/76 , H01L29/745
CPC分类号： H01L31/101 , H01L27/14647 , H01L31/1804 , Y02E10/547 , Y02P70/521
摘要： An optical sensor and method for forming the same. The optical sensor structure includes (a) a semiconductor substrate, (b) first, second, third, fourth, fifth, and sixth electrodes and (c) first, second, and third semiconducting regions. The first and fourth electrodes are at a first depth. The second and fifth electrodes are at a second depth. The third and sixth electrodes are at a third depth. The first depth is greater than the second depth, and the second depth is greater than the third depth. The first, second, and third semiconducting regions are disposed between and in contact with the first and fourth electrodes, second and fifth electrodes, and third and sixth electrodes, respectively. The first, second, and third semiconducting regions are in contact with each other.
摘要翻译：一种光学传感器及其形成方法。光学传感器结构包括（a）半导体衬底，（b）第一，第二，第三，第四，第五和第六电极以及（c）第一，第二和第三半导电区域。第一和第四电极处于第一深度。第二和第五电极处于第二深度。第三和第六电极处于第三深度。第一深度大于第二深度，第二深度大于第三深度。第一，第二和第三半导体区域分别设置在第一和第四电极，第二和第五电极以及第三和第六电极之间并与之接触。第一，第二和第三半导电区域彼此接触。

135. 发明授权

US07217604B2 Structure and method for thin box SOI device 有权
标题翻译：薄盒SOI器件的结构和方法
公开(公告)号：US07217604B2
公开(公告)日：2007-05-15
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
发明人： Toshiharu Furukawa , Carl J. Radens , William R. Tonti , Richard Q. Williams
IPC分类号： H01L21/84
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, including providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

136. 发明申请

US20070059894A1 SELECTIVE DEPOSITION OF GERMANIUM SPACERS ON NITRIDE 失效
标题翻译：硝酸盐选择性沉积氮离子
公开(公告)号：US20070059894A1
公开(公告)日：2007-03-15
申请号：US10905587
申请日：2005-09-12
申请人： Ashima Chakravarti , Anthony Chou , Toshiharu Furukawa , Steven Holmes , Wesley Natzle
发明人： Ashima Chakravarti , Anthony Chou , Toshiharu Furukawa , Steven Holmes , Wesley Natzle
IPC分类号： H01L21/336 , H01L21/44 , H01L21/20
CPC分类号： H01L29/7833 , H01L21/02532 , H01L21/02587 , H01L21/0262 , H01L21/02639 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L2224/05571 , H01L2224/05573 , H01L2224/10126 , H01L2224/13023 , H01L2924/1305 , H01L2924/00
摘要： A method of selectively forming a germanium structure within semiconductor manufacturing processes removes the native oxide from a nitride surface in a chemical oxide removal (COR) process and then exposes the heated nitride and oxide surface to a heated germanium containing gas to selectively form germanium only on the nitride surface but not the oxide surface.
摘要翻译：在半导体制造工艺中选择性地形成锗结构的方法在化学氧化物去除（COR）工艺中从氮化物表面去除天然氧化物，然后将加热的氮化物和氧化物表面暴露于加热的含锗气体，以仅选择性地形成锗氮化物表面而不是氧化物表面。

137. 发明申请

US20070023839A1 FINFET GATE FORMED OF CARBON NANOTUBES 审中-公开
标题翻译：碳纳米管的FINFET栅组成
公开(公告)号：US20070023839A1
公开(公告)日：2007-02-01
申请号：US11161219
申请日：2005-07-27
申请人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
发明人： Toshiharu Furukawa , Mark Hakey , Steven Holmes , David Horak , Charles Koburger
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , B82Y10/00 , H01L29/4908 , H01L29/66795 , H01L51/0048 , H01L51/0512
摘要： A fin field effect transistor (FinFET) gate comprises a semiconductor wafer; a gate dielectric layer over the semiconductor wafer; a conductive material on the gate dielectric layer; an activated carbon nanotube on a surface of the conductive material; and a plated metal layer on the activated carbon nanotube. Preferably, the carbon nanotube is on a sidewall of the conductive material. The conductive material comprises a first metal layer over the gate dielectric layer, wherein the first metal layer acts as a catalyst for growing the carbon nanotube, wherein the first metal layer is preferably in a range of 1-10 nm in thickness. The semiconductor wafer may comprise a silicon on insulator wafer. The FinFET gate may further comprise a second metal layer disposed between the first metal layer and the gate dielectric layer.
摘要翻译：鳍状场效应晶体管（FinFET）栅极包括半导体晶片; 半导体晶片上的栅介质层; 栅介电层上的导电材料; 导电材料表面上的活性炭纳米管; 和活化碳纳米管上的电镀金属层。优选地，碳纳米管位于导电材料的侧壁上。导电材料包括在栅极介电层上的第一金属层，其中第一金属层用作生长碳纳米管的催化剂，其中第一金属层的厚度优选在1-10nm的范围内。半导体晶片可以包括绝缘体上硅晶片。 FinFET栅极还可以包括设置在第一金属层和栅极介电层之间的第二金属层。

138. 发明申请

US20060231892A1 Enhanced silicon-on-insulator (SOI) transistors and methods of making enhanced SOI transistors 失效
标题翻译：增强的绝缘体上硅（SOI）晶体管和制造增强型SOI晶体管的方法
公开(公告)号：US20060231892A1
公开(公告)日：2006-10-19
申请号：US11106002
申请日：2005-04-14
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L27/12
CPC分类号： H01L29/78687 , H01L21/26533 , H01L21/84 , H01L27/1203 , H01L29/165 , H01L29/66545 , H01L29/66772 , H01L29/7842 , H01L29/7848 , H01L29/78603
摘要： Enhanced silicon-on-insulator transistors and methods are provided for implementing enhanced silicon-on-insulator transistors. The enhanced silicon-on-insulator (SOI) transistors include a thin buried oxide (BOX) layer under a device channel and a thick self-aligned buried oxide (BOX) region under SOI source/drain diffusions. A selective epitaxial growth is utilized in the source/drain regions to implement appropriate strain to enhance both PFET and NFET devices simultaneously.
摘要翻译：提供了增强的绝缘体上硅晶体管和方法，用于实现增强的绝缘体上硅晶体管。增强型绝缘体上硅（SOI）晶体管包括在SOI源极/漏极扩散下的器件沟道下的薄的掩埋氧化物（BOX）层和厚的自对准埋氧（BOX）区。在源极/漏极区域中使用选择性外延生长来实现适当的应变以同时增强PFET和NFET器件。

139. 发明申请

US20060186416A1 MULTIPLE LAYER AND CRYSTAL PLANE ORIENTATION SEMICONDUCTOR SUBSTRATE 有权
标题翻译：多层和晶体平面取向半导体基板
公开(公告)号：US20060186416A1
公开(公告)日：2006-08-24
申请号：US10906557
申请日：2005-02-24
申请人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
发明人： Toshiharu Furukawa , David Horak , Charles Koburger , Leathen Shi
IPC分类号： H01L29/15 , H01L31/0312
CPC分类号： H01L29/045 , H01L21/76254 , H01L21/823807 , H01L27/1203
摘要： A semiconductor on insulator substrate and a method of fabricating the substrate. The substrate including: a first crystalline semiconductor layer and a second crystalline semiconductor layer; and an insulating layer bonding a bottom surface of the first crystalline semiconductor layer to a top surface of the second crystalline semiconductor layer, a first crystal direction of the first crystalline semiconductor layer aligned relative to a second crystal direction of the second crystalline semiconductor layer, the first crystal direction different from the second crystal direction.
摘要翻译：绝缘体上半导体衬底及其制造方法。所述基板包括：第一晶体半导体层和第二晶体半导体层; 以及将所述第一晶体半导体层的底面与所述第二结晶半导体层的顶面接合的绝缘层，所述第一结晶半导体层相对于所述第二结晶半导体层的第二晶体方向排列的第一晶体方向，第一晶体方向与第二晶体方向不同。

140. 发明申请

US20060172499A1 STRUCTURE AND METHOD FOR THIN BOX SOI DEVICE 有权
标题翻译：薄盒SOI器件的结构与方法
公开(公告)号：US20060172499A1
公开(公告)日：2006-08-03
申请号：US10906014
申请日：2005-01-31
申请人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
发明人： Toshiharu Furukawa , Carl Radens , William Tonti , Richard Williams
IPC分类号： H01L21/336
CPC分类号： H01L29/66772 , H01L29/665 , H01L29/78606 , H01L29/78612
摘要： A method of forming a semiconductor device, comprising providing a substrate having a first insulative layer on a surface of the substrate, and a device layer on a surface of the first insulative layer, forming a spacer around the first insulative layer and the device layer, removing a portion of the substrate adjacent to the first insulative layer in a first region and a non-adjacent second region of the substrate, such that an opening is formed in the first and second regions of the substrate, leaving the substrate adjacent to the first insulative layer in a third region of the substrate, filling the opening within the first and second regions of the substrate, planarizing a surface of the device, and forming a device within the device layer, such that diffusion regions of the device are formed within the device layer above the first and second regions of the substrate, and a channel region of the device is formed above the third region of the substrate.
摘要翻译：一种形成半导体器件的方法，包括在所述衬底的表面上提供具有第一绝缘层的衬底以及在所述第一绝缘层的表面上的器件层，在所述第一绝缘层和所述器件层周围形成间隔物，在衬底的第一区域和不相邻的第二区域中移除邻近第一绝缘层的衬底的一部分，使得在衬底的第一和第二区域中形成开口，使衬底与第一绝缘层相邻，在衬底的第三区域中的绝缘层，填充衬底的第一和第二区域内的开口，使器件的表面平坦化，以及在器件层内形成器件，使得器件的扩散区域形成在器件层在衬底的第一和第二区域之上，并且器件的沟道区形成在衬底的第三区域上方。

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