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121. 发明授权

US08309447B2 Method for integrating multiple threshold voltage devices for CMOS 有权
标题翻译：用于集成多个CMOS阈值电压器件的方法
公开(公告)号：US08309447B2
公开(公告)日：2012-11-13
申请号：US12855273
申请日：2010-08-12
申请人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
发明人： Kangguo Cheng , Bruce B. Doris , Lisa F. Edge , Balasubramanian S. Haran , Hemanth Jagannathan , Ali Khakifirooz , Vamsi K. Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823857 , H01L21/823462 , H01L21/823481 , H01L21/823878
摘要： A method to achieve multiple threshold voltage (Vt) devices on the same semiconductor chip is disclosed. The method provides different threshold voltage devices using threshold voltage adjusting materials and a subsequent drive in anneal instead of directly doping the channel. As such, the method of the present disclosure avoids short channel penalties. Additionally, no ground plane/back gates are utilized in the present application thereby the method of the present disclosure can be easily integrated into current complementary metal oxide semiconductor (CMOS) processing technology.
摘要翻译：公开了在同一半导体芯片上实现多个阈值电压（Vt）器件的方法。该方法提供使用阈值电压调节材料的不同阈值电压器件，以及随后的退火驱动而不是直接掺杂通道。因此，本公开的方法避免了短信道惩罚。此外，在本申请中没有使用接地平面/后门，因此本公开的方法可以容易地集成到电流互补金属氧化物半导体（CMOS）处理技术中。

122. 发明申请

US20120261757A1 STRAINED THIN BODY CMOS DEVICE HAVING VERTICALLY RAISED SOURCE/DRAIN STRESSORS WITH SINGLE SPACER 有权
标题翻译：具有单个间距的垂直源/源压应力的应变薄体CMOS器件
公开(公告)号：US20120261757A1
公开(公告)日：2012-10-18
申请号：US13531053
申请日：2012-06-22
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L29/78 , H01L27/092
CPC分类号： H01L29/66477 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203 , H01L29/66628 , H01L29/66772 , H01L29/7848 , H01L29/78618
摘要： A method of forming a transistor device includes forming a patterned gate structure over a semiconductor substrate; forming a spacer layer over the semiconductor substrate and patterned gate structure; removing horizontally disposed portions of the spacer layer so as to form a vertical sidewall spacer adjacent the patterned gate structure; and forming a raised source/drain (RSD) structure over the semiconductor substrate and adjacent the vertical sidewall spacer, wherein the RSD structure has a substantially vertical sidewall profile so as to abut the vertical sidewall spacer and produce one of a compressive and a tensile strain on a channel region of the semiconductor substrate below the patterned gate structure.
摘要翻译：一种形成晶体管器件的方法包括在半导体衬底上形成图案化栅极结构; 在半导体衬底上形成间隔层和图案化栅极结构; 去除间隔层的水平设置部分，以形成邻近图案化栅极结构的垂直侧壁间隔物; 以及在所述半导体衬底上并且邻近所述垂直侧壁间隔物形成升高的源极/漏极（RSD）结构，其中所述RSD结构具有基本上垂直的侧壁轮廓，以便邻接所述垂直侧壁间隔物并产生压缩和拉伸应变之一在图案化的栅极结构下方的半导体衬底的沟道区上。

123. 发明授权

US08215074B2 Pattern formation employing self-assembled material 有权
标题翻译：采用自组装材料的图案形成
公开(公告)号：US08215074B2
公开(公告)日：2012-07-10
申请号：US12026123
申请日：2008-02-05
申请人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl Radens
发明人： Charles T. Black , Timothy J. Dalton , Bruce B. Doris , Carl Radens
IPC分类号： E04B2/00
CPC分类号： H01L21/0338 , B81B2203/0369 , B81C1/00031 , B81C2201/0149 , B81C2201/0198 , B82Y30/00 , H01L21/0337 , H01L51/0017 , Y10S977/882 , Y10S977/887 , Y10S977/888 , Y10T428/24479 , Y10T428/2457 , Y10T428/24612 , Y10T428/24736 , Y10T428/24802
摘要： In one embodiment, Hexagonal tiles encompassing a large are divided into three groups, each containing ⅓ of all hexagonal tiles that are disjoined among one another. Openings for the hexagonal tiles in each group are formed in a template layer, and a set of self-assembling block copolymers is applied and patterned within each opening. This process is repeated three times to encompass all three groups, resulting in a self-aligned pattern extending over a wide area. In another embodiment, the large area is divided into rectangular tiles of two non-overlapping and complementary groups. Each rectangular area has a width less than the range of order of self-assembling block copolymers. Self-assembled self-aligned line and space structures are formed in each group in a sequential manner so that a line and space pattern is formed over a large area extending beyond the range of order.
摘要翻译：在一个实施例中，包括大的六边形瓦片被分成三组，每组包含彼此分离的所有六边形瓦片的1/3。每个组中的六边形瓦片的开口形成在模板层中，并且在每个开口内施加并组合一组自组装嵌段共聚物。该过程重复三次以包含所有三组，导致在大面积上延伸的自对准图案。在另一个实施例中，大面积被分成两个不重叠和互补组的矩形瓦片。每个矩形区域的宽度小于自组装嵌段共聚物的顺序范围。在每组中以顺序的方式形成自组装的自对准线和空间结构，使得在超过有序范围的大面积上形成线和空间图案。

124. 发明申请

US20120132966A1 SEMICONDUCTOR STRUCTURES HAVING IMPROVED CONTACT RESISTANCE 有权
标题翻译：具有改善接触电阻的半导体结构
公开(公告)号：US20120132966A1
公开(公告)日：2012-05-31
申请号：US11872291
申请日：2007-10-15
申请人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
发明人： Bruce B. Doris , Carl J. Radens , Anthony K. Stamper , Jay W. Strane
IPC分类号： H01L29/78 , H01L21/768 , H01L23/52
CPC分类号： H01L21/28518 , B81B2207/07 , B81C1/00095 , B81C2201/0149 , H01L21/3086 , H01L21/76886 , H01L23/485 , H01L23/5226 , H01L29/41766 , H01L29/665 , H01L29/66636 , H01L2924/0002 , H01L2924/00
摘要： Self-assembled polymer technology is used to form at least one ordered nanosized pattern within material that is present in a conductive contact region of a semiconductor structure. The material having the ordered, nanosized pattern is a conductive material of an interconnect structure or semiconductor source and drain diffusion regions of a field effect transistor. The presence of the ordered, nanosized pattern material within the contact region increases the overall area (i.e., interface area) for subsequent contact formation which, in turn, reduces the contact resistance of the structure. The reduction in contact resistance in turn improves the flow of current through the structure. In addition to the above, the inventive methods and structures do not affect the junction capacitance of the structure since the junction area remains unchanged.
摘要翻译：自组装聚合物技术用于在存在于半导体结构的导电接触区域中的材料内形成至少一个有序的纳米尺度图案。具有有序纳米尺寸图案的材料是场效应晶体管的互连结构或半导体源和漏极扩散区的导电材料。在接触区域内有序的纳米尺寸图案材料的存在增加了用于随后的接触形成的总面积（即界面面积），这又降低了结构的接触电阻。接触电阻的降低又改善了通过结构的电流的流动。除了上述之外，本发明的方法和结构不影响结构的结电容，因为结面积保持不变。

125. 发明授权

US08187961B2 Threshold adjustment for high-K gate dielectric CMOS 有权
标题翻译：高K栅极电介质CMOS的阈值调整
公开(公告)号：US08187961B2
公开(公告)日：2012-05-29
申请号：US12535554
申请日：2009-08-04
申请人： Bruce B. Doris , Eduard Albert Cartier , Vijay Narayanan , Vamsi Paruchuri
发明人： Bruce B. Doris , Eduard Albert Cartier , Vijay Narayanan , Vamsi Paruchuri
IPC分类号： H01L21/3205 , H01L21/4763
CPC分类号： H01L21/823864 , H01L21/28176 , H01L27/092 , H01L29/6656 , Y10S438/981
摘要： A CMOS structure is disclosed in which a first type FET has an extremely thin oxide liner. This thin liner is capable of preventing oxygen from reaching the high-k dielectric gate insulator of the first type FET. A second type FET device of the CMOS structure has a thicker oxide liner. As a result, an oxygen exposure is capable to shift the threshold voltage of the second type of FET, without affecting the threshold value of the first type FET. The disclosure also teaches methods for producing the CMOS structure in which differing type of FET devices have differing thickness liners, and the threshold values of the differing type of FET devices is set independently from one another.
摘要翻译：公开了一种CMOS结构，其中第一类型FET具有极薄的氧化物衬垫。该薄衬套能够防止氧气到达第一类型FET的高k电介质栅极绝缘体。 CMOS结构的第二种FET器件具有较厚的氧化物衬垫。结果，氧暴露能够移动第二类型FET的阈值电压，而不影响第一类型FET的阈值。本公开还教导了用于制造CMOS结构的方法，其中不同类型的FET器件具有不同的厚度衬垫，并且不同类型的FET器件的阈值彼此独立地设置。

126. 发明申请

US20120129357A1 TWO-DIMENSIONAL PATTERNING EMPLOYING SELF-ASSEMBLED MATERIAL 有权
标题翻译：使用自组装材料的二维图案
公开(公告)号：US20120129357A1
公开(公告)日：2012-05-24
申请号：US12017598
申请日：2008-01-22
申请人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
发明人： Timothy J. Dalton , Bruce B. Doris , Ho-Cheol Kim , Carl Radens
IPC分类号： H01L21/31 , B82Y40/00
CPC分类号： H01L21/0337 , B81C1/00031 , B81C2201/0149 , B82Y10/00 , B82Y30/00 , H01L21/0338 , Y10T428/24612
摘要： A first nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running along a first direction is formed from first self-assembling block copolymers within a first layer. The first layer is filled with a filler material and a second layer is deposited above the first layer containing the first nanoscale nested line structure. A second nanoscale self-aligned self-assembled nested line structure having a sublithographic width and a sublithographic spacing and running in a second direction is formed from second self-assembling block copolymers within the second layer. The composite pattern of the first nanoscale nested line structure and the second nanoscale nested line structure is transferred into an underlayer beneath the first layer to form an array of structures containing periodicity in two directions.
摘要翻译：具有亚光刻宽度和亚光刻距离并沿着第一方向延伸的第一纳米级自对准自组装嵌套线结构由第一层内的第一自组装嵌段共聚物形成。第一层填充有填充材料，并且第二层沉积在包含第一纳米级嵌套线结构的第一层之上。具有亚光刻宽度和亚光刻距离并沿第二方向运行的第二纳米级自对准自组装嵌套线结构由第二层内的第二自组装嵌段共聚物形成。第一纳米级嵌套线结构和第二纳米级嵌套线结构的复合图案被转移到第一层下面的底层中以形成在两个方向上包含周期性的结构阵列。

127. 发明申请

US20120086071A1 STRESS MEMORIZATION PROCESS IMPROVEMENT FOR IMPROVED TECHNOLOGY PERFORMANCE 有权
标题翻译：应力记忆过程改进改进的技术性能
公开(公告)号：US20120086071A1
公开(公告)日：2012-04-12
申请号：US12902624
申请日：2010-10-12
申请人： Lahir Shaik Adam , Bruce B. Doris , Sanjay Mehta , Zhengmao Zhu
发明人： Lahir Shaik Adam , Bruce B. Doris , Sanjay Mehta , Zhengmao Zhu
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/7847
摘要： Semiconductor substrate with a deformed gate region and a method for the fabrication thereof. The semiconductor substrate has improved device performance compared to devices without a deformed gate region and decreased dopant loss compared to devices with deformed source/drain regions.
摘要翻译：具有变形栅极区域的半导体衬底及其制造方法。与具有变形的源极/漏极区域的器件相比，半导体衬底与不具有变形栅极区域的器件相比具有改进的器件性能和降低的掺杂剂损耗。

128. 发明申请

US20120068267A1 STRAINED DEVICES, METHODS OF MANUFACTURE AND DESIGN STRUCTURES 有权
公开(公告)号：US20120068267A1
公开(公告)日：2012-03-22
申请号：US12886881
申请日：2010-09-21
申请人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
发明人： Stephen W. Bedell , Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Katherine L. Saenger
IPC分类号： H01L29/786 , H01L21/762
CPC分类号： H01L21/84 , H01L21/823807
摘要： Strained Si and strained SiGe on insulator devices, methods of manufacture and design structures is provided. The method includes growing an SiGe layer on a silicon on insulator wafer. The method further includes patterning the SiGe layer into PFET and NFET regions such that a strain in the SiGe layer in the PFET and NFET regions is relaxed. The method further includes amorphizing by ion implantation at least a portion of an Si layer directly underneath the SiGe layer. The method further includes performing a thermal anneal to recrystallize the Si layer such that a lattice constant is matched to that of the relaxed SiGe, thereby creating a tensile strain on the NFET region. The method further includes removing the SiGe layer from the NFET region. The method further includes performing a Ge process to convert the Si layer in the PFET region into compressively strained SiGe.

129. 发明授权

US08138543B2 Hybrid FinFET/planar SOI FETs 有权
标题翻译：混合FinFET /平面SOI FET
公开(公告)号：US08138543B2
公开(公告)日：2012-03-20
申请号：US12621460
申请日：2009-11-18
申请人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ghavam G. Shahidi
IPC分类号： H01L27/01
CPC分类号： H01L21/845 , H01L21/823807 , H01L21/823878 , H01L27/1211 , H01L29/785
摘要： A circuit structure is disclosed which contains least one each of three different kinds of devices in a silicon layer on insulator (SOI): a planar NFET device, a planar PFET device, and a FinFET device. A trench isolation surrounds the planar NFET device and the planar PFET device penetrating through the SOI and abutting the insulator. Each of the three different kinds of devices contain a high-k gate dielectric layer and a mid-gap gate metal layer, each containing an identical high-k material and an identical mid-gap metal. Each of the three different kinds of devices have an individually optimized threshold value. A method for fabricating a circuit structure is also disclosed, which method involves defining portions in SOI respectively for three different kinds of devices: for a planar NFET device, for a planar PFET device, and for a FinFET device. The method also includes depositing in common a high-k gate dielectric layer and a mid-gap gate metal layer, and using workfunction modifying layers to individually adjust thresholds for the various kinds of devices.
摘要翻译：公开了一种电路结构，其包含绝缘体上硅层（SOI）中的三种不同类型的器件中的至少一种：平面NFET器件，平面PFET器件和FinFET器件。沟槽隔离围绕平面NFET器件，并且平面PFET器件穿透SOI并邻接绝缘体。三种不同类型的器件中的每一种都包含高k栅极电介质层和中间间隙栅极金属层，每个包含相同的高k材料和相同的中间间隙金属。三种不同类型的设备中的每一种具有单独优化的阈值。还公开了一种用于制造电路结构的方法，该方法包括为三种不同类型的器件分别定义SOI中的部分：对于平面NFET器件，用于平面PFET器件和FinFET器件。该方法还包括共同沉积高k栅极电介质层和中间间隙栅极金属层，并且使用功函数修改层来单独调节各种器件的阈值。

130. 发明申请

US20120061759A1 Extremely Thin Semiconductor-on-Insulator (ETSOI) FET Having a Stair-Shape Raised Source/Drain and a Method of Forming the Same 有权
标题翻译：极薄的绝缘体上半导体（ETSOI）FET，具有阶梯式引出源/漏极及其形成方法
公开(公告)号：US20120061759A1
公开(公告)日：2012-03-15
申请号：US12882490
申请日：2010-09-15
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ghavam Shahidi
IPC分类号： H01L29/786 , H01L21/782
CPC分类号： H01L29/78654 , H01L29/66628 , H01L29/66772
摘要： A MOSFET device is formed on top of a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness ranging from 3 nm to 20 nm. A stair-shape raised extension, a raised source region and a raised drain region (S/D) are formed on top of the SOI substrate. The thinner raised extension region abuts at a thin gate sidewall spacer, lowering the extension resistance without significantly increasing the parasitic resistance. A single epitaxial growth forms the thinner raised extension and the thicker raised S/D preferably simultaneously, reducing the fabrication cost as well as the contact resistance between the raised S/D and the extension. A method of forming the aforementioned MOSFET device is also provided.
摘要翻译：在具有厚度范围为3nm至20nm的半导体层的绝缘体上半导体（SOI）衬底的顶部上形成MOSFET器件。在SOI衬底的顶部上形成阶梯形凸起的延伸部，凸起的源极区域和凸起的漏极区域（S / D）。更薄的凸起的延伸区域邻近薄的栅极侧壁间隔物，降低延伸电阻而不显着增加寄生电阻。单个外延生长优选同时形成更薄的凸起延伸和较高的凸起S / D，从而降低制造成本以及升高的S / D与延伸部之间的接触电阻。还提供了形成上述MOSFET器件的方法。

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