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121. 发明申请

US20080284021A1 Method for FEOL and BEOL Wiring 失效
标题翻译： FEOL和BEOL接线方法
公开(公告)号：US20080284021A1
公开(公告)日：2008-11-20
申请号：US11749898
申请日：2007-05-17
申请人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
发明人： Brent A. Anderson , John J. Ellis-Monaghan , Edward J. Nowak , Jed H. Rankin
IPC分类号： H01L21/44 , H01L23/48
CPC分类号： H01L21/76885 , H01L21/76843 , H01L21/76844 , H01L21/76867 , H01L21/76895 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a conductive structure of sub-lithographic dimension suitable for FEOL and BEOL semiconductor fabrication applications. The method includes forming a topographic feature of silicon-containing material on a substrate; forming a dielectric cap on the topographic feature; applying a mask structure to expose a pattern on a sidewall of the topographic feature, the exposed pattern corresponding to a conductive structure to be formed; depositing a metal at the exposed portions of the sidewall and forming one or more metal silicide conductive structures at the exposed sidewall portions; removing the dielectric cap layer; and removing the silicon-containing topographic feature. The result is the formation of one or more metal silicide conductor structures formed for a single lithographically defined feature. In example embodiments, the formed metal silicide conductive structures have a high aspect ratio, e.g., ranging from 1:1 to 20:1 (height to width dimension).
摘要翻译：一种用于形成适用于FEOL和BEOL半导体制造应用的亚光刻尺寸的导电结构的方法。该方法包括在衬底上形成含硅材料的形貌特征; 在地形特征上形成介电帽; 施加掩模结构以暴露所述地形特征的侧壁上的图案，所述暴露图案对应于要形成的导电结构; 在所述侧壁的暴露部分处沉积金属并在所述暴露的侧壁部分处形成一个或多个金属硅化物导电结构; 去除所述电介质盖层; 并去除含硅的地形特征。结果是形成一个或多个金属硅化物导体结构，其形成用于单个光刻定义的特征。在示例性实施例中，形成的金属硅化物导电结构具有高纵横比，例如从1：1至20：1（高度与宽度尺寸）。

122. 发明申请

US20080272399A1 PIXEL SENSOR CELL FOR COLLECTING ELECTRONS AND HOLES 有权
公开(公告)号：US20080272399A1
公开(公告)日：2008-11-06
申请号：US12172305
申请日：2008-07-14
申请人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
发明人： James W. Adkisson , Andres Bryant , John J. Ellis-Monaghan , Mark D. Jaffe , Jeffrey B. Johnson , Alain Loiseau
IPC分类号： H01L31/00
CPC分类号： H01L27/14603 , H01L27/14609 , H01L27/14689 , H01L31/035281
摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

123. 发明授权

US07445966B2 Method and structure for charge dissipation during fabrication of integrated circuits and isolation thereof 有权
标题翻译：集成电路制造期间电荷耗散的方法和结构及其分离
公开(公告)号：US07445966B2
公开(公告)日：2008-11-04
申请号：US11160468
申请日：2005-06-24
申请人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Timothy D. Sullivan , Steven H. Voldman
发明人： John J. Ellis-Monaghan , Jeffrey P. Gambino , Timothy D. Sullivan , Steven H. Voldman
IPC分类号： H01L23/60
CPC分类号： H01L27/0248 , Y10S438/926
摘要： A method, structure and design method for dissipating charge during fabrication of an integrated circuit. The structure includes: a substrate contact in a substrate; one or more wiring levels over the substrate; one or more electrically conductive charge dissipation structures extending from a top surface of an uppermost wiring level of the one or more wiring levels through each lower wiring level of the one or more wiring levels to and in electrical contact with the substrate contact; and circuit structures in the substrate and in the one or more wiring layers, the charge dissipation structures not electrically contacting any the circuit structures in any of the one or more wiring levels, the one or more charge dissipation structures dispersed between the circuit structures.
摘要翻译：一种用于在集成电路制造期间耗散电荷的方法，结构和设计方法。该结构包括：衬底中的衬底接触; 衬底上的一个或多个布线层; 一个或多个导电电荷耗散结构，其从所述一个或多个布线层的最上层布线层的顶表面延伸通过所述一个或多个布线层的每个下布线层与所述基板接触电接触; 以及在基板中和在一个或多个布线层中的电路结构，电荷耗散结构在电路结构之间分散的一个或多个电荷耗散结构不会电接触任何一个或多个布线层中的任何一个电路结构。

124. 发明授权

US07138691B2 Selective nitridation of gate oxides 有权
标题翻译：选择性氮化栅氧化物
公开(公告)号：US07138691B2
公开(公告)日：2006-11-21
申请号：US10707897
申请日：2004-01-22
申请人： Jay S. Burnham , John J. Ellis-Monaghan , James S. Nakos , James J. Quinlivan
发明人： Jay S. Burnham , John J. Ellis-Monaghan , James S. Nakos , James J. Quinlivan
IPC分类号： H01L29/76
CPC分类号： H01L21/823857
摘要： A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.
摘要翻译：半导体结构包括已经选择性地富氮的薄栅极电介质。引入的氮气量足以减少或防止栅极泄漏和掺杂剂渗透，而不会明显降低器件性能。较低浓度的氮被引入到pFET栅极电介质中，而不是nFET栅极电介质。氮化可以通过各种技术选择性地完成，包括快速热氮化（RTN），炉氮化，远程等离子体氮化（RPN），去耦等离子体氮化（DPN），阱注入和/或多晶硅注入。

125. 发明授权

US06964906B2 Programmable element with selectively conductive dopant and method for programming same 失效
标题翻译：具有选择性导电掺杂剂的可编程元件及其编程方法
公开(公告)号：US06964906B2
公开(公告)日：2005-11-15
申请号：US10064317
申请日：2002-07-02
申请人： Patricia S. Bunt , John J. Ellis-Monaghan
发明人： Patricia S. Bunt , John J. Ellis-Monaghan
IPC分类号： H01L27/10 , H01L21/336
CPC分类号： H01L27/101
摘要： A programmable element including a semiconductor material doped with a dopant that alters the resistance of the element when exposed to actinic radiation. Rather than producing a mechanical deformation, the radiation rearranges the bonding configuration of the dopant in the element, allowing it to be placed on a chip in close proximity to other device structures without risking damage to those structures. After formation, the programmable element is subjected to a laser anneal process in which the dopant is electrically activated. The activation process allows the dopant to donate a charge carrier to the crystal structure. Rapid cooling following laser anneal preserves the desired bonding configuration of the dopant produced in the programmable element. Laser anneals have been shown to reduce the resistivity of a programmable element by at least a factor of two.
摘要翻译：一种可编程元件，包括掺杂有掺杂剂的半导体材料，其在暴露于光化辐射时改变元件的电阻。辐射不是产生机械变形，而是重新排列元件中的掺杂剂的结合构型，使得它可以放置在紧靠其他器件结构的芯片上，而不会对这些结构造成损害。在形成之后，对可编程元件进行激光退火处理，其中掺杂剂被电激活。激活过程允许掺杂剂将电荷载体提供给晶体结构。激光退火后的快速冷却保留了在可编程元件中产生的掺杂剂所需的接合结构。激光退火已被证明可以将可编程元件的电阻率降低至少两倍。

126. 发明授权

US06482660B2 Effective channel length control using ion implant feed forward 有权
标题翻译：有效的通道长度控制使用离子注入前馈
公开(公告)号：US06482660B2
公开(公告)日：2002-11-19
申请号：US09812006
申请日：2001-03-19
申请人： Brian P. Conchieri , Steven M. Ruegsegger , John J. Ellis-Monaghan
发明人： Brian P. Conchieri , Steven M. Ruegsegger , John J. Ellis-Monaghan
IPC分类号： H01L2100
CPC分类号： H01L22/20
摘要： The present invention discloses the use of ion implant recipe changes to control the effective channel length by compensating for any variation in the gate electrode width. The invention provides a method for controlling the effective channel length in FETs by measuring the gate electrode width, sending the measured gate electrode width to an ion implant controller, calculating a desired ion implant condition which compensates for any deviation in the effective channel length from target, and subsequently selecting or generating an ion implant recipe based on the desired conditions. Such ion implant recipe is then implanted into the FET to control the effective channel length by defining the halo, LDD, source, drain, or any other doped regions of the device which define the effective channel length, thereby resulting in a manufacturing process with higher yields and less scrap.
摘要翻译：本发明公开了通过补偿栅电极宽度的任何变化来使用离子注入配方改变来控制有效沟道长度。本发明提供了一种用于通过测量栅电极宽度来控制FET中的有效沟道长度的方法，将测量的栅电极宽度发送到离子注入控制器，计算期望的离子注入条件，其补偿有效沟道长度与目标的任何偏差，并且随后基于期望的条件选择或生成离子植入物配方。然后将这样的离子注入配方注入到FET中以通过限定限定有效通道长度的器件的卤素，LDD，源极，漏极或任何其它掺杂区域来控制有效沟道长度，由此导致制造过程具有更高的产量和少量废料。

127. 发明授权

US06417515B1 In-situ ion implant activation and measurement apparatus 有权
标题翻译：原位离子注入激活和测量装置
公开(公告)号：US06417515B1
公开(公告)日：2002-07-09
申请号：US09527192
申请日：2000-03-17
申请人： Howard T. Barrett , John J. Ellis-Monaghan , Toshiharu Furukawa , James A. Slinkman
发明人： Howard T. Barrett , John J. Ellis-Monaghan , Toshiharu Furukawa , James A. Slinkman
IPC分类号： H01J37317
CPC分类号： H01J37/3171 , H01J2237/30466 , H01J2237/31703
摘要： A substrate, such as a semiconductor chip or wafer, is implanted along with product wafers in an ion implant vacuum system. The substrate is then annealed in an annealing step that is accomplished while the substrate is within the vacuum system. The annealer is a rapid thermal annealer, such as a laser annealer or a flash lamp annealer. The annealing step does not affect the product wafers. Then a measurement is performed on the implanted and annealed substrate while it is within the vacuum system that can be suitably correlated with implant dose. The measurement can be with a technique such as a four point probe or with a tool that measures optical reflectivity from a surface of the implanted substrate. An additional implant can then be provided to product wafers if necessary to come closer to the desired dose.
摘要翻译：将衬底（例如半导体芯片或晶片）与产品晶片一起植入离子注入真空系统中。然后在基板处于真空系统内的退火步骤中退火基板。退火炉是快速热退火炉，例如激光退火炉或闪光灯退火炉。退火步骤不影响产品晶圆。然后对植入和退火的基底进行测量，同时它在可以适当地与植入剂量相关联的真空系统内。该测量可以采用诸如四点探针的技术或者用来测量从植入的衬底的表面的光学反射率的工具。如果需要，可以将另外的植入物提供给产品晶片以更接近所需剂量。

128. 发明授权

US06300228B1 Multiple precipitation doping process 失效
标题翻译：多重沉淀掺杂工艺
公开(公告)号：US06300228B1
公开(公告)日：2001-10-09
申请号：US09386089
申请日：1999-08-30
申请人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
发明人： James W. Adkisson , James A. Bruce , John J. Ellis-Monaghan , Randy W. Mann , Edward J. Nowak , Kirk D. Peterson
IPC分类号： H01L2122
CPC分类号： H01L21/268 , H01L21/0455 , H01L21/2255
摘要： A multiple precipitation doping process for doping a semiconductor substrate (30) starts with forming an amorphous region (32) in the substrate (30). Through multiple laser exposures, multiple dopant precipitation films (52, 53) are formed on corresponding portions (34, 37) of the major surface (31) of the substrate (30) overlying the amorphous region (32). The substrate (30) is then annealed. The annealing process melts the amorphous region (32) and allows the dopants precipitated on the major surface (31) to diffuse into the substrate (30). The annealing process also crystallizes the semiconductor material the amorphous region (32). The substrate (30) becomes a single crystal semiconductor substrate with multiple doped regions (54, 57) therein. The depth of the doped regions (54, 57) is substantially equal to the depth of the amorphous region (32) before annealing.
摘要翻译：用于掺杂半导体衬底（30）的多次沉淀掺杂工艺从在衬底（30）中形成无定形区域（32）开始。通过多次激光曝光，在覆盖非晶区域（32）的衬底（30）的主表面（31）的相应部分（34,37）上形成多个掺杂剂沉淀膜（52,53）。然后将衬底（30）退火。退火过程熔化非晶区域（32）并且允许沉淀在主表面（31）上的掺杂剂扩散到衬底（30）中。退火过程也使非晶区域（32）半导体材料结晶。基板（30）成为具有多个掺杂区域（54,57）的单晶半导体基板。掺杂区域（54,57）的深度基本上等于退火前非晶区域（32）的深度。

129. 发明授权

US6040991A SRAM memory cell having reduced surface area 失效
标题翻译：具有减小的表面积的SRAM存储单元
公开(公告)号：US6040991A
公开(公告)日：2000-03-21
申请号：US225074
申请日：1999-01-04
申请人： John J. Ellis-Monaghan , Wilbur D. Pricer
发明人： John J. Ellis-Monaghan , Wilbur D. Pricer
IPC分类号： G11C11/412 , H01L21/8244 , H01L27/11 , G11C11/00
CPC分类号： G11C11/412
摘要： A Static RAM cell having a reduced surface area. The Static RAM cell includes a pair of P channel transistors and a pair of N channel transistors connected as a bistable latch. A first common source connection of the latch is connected to a Write Bit terminal and the remaining source connections of the latch are connected to complementary bit lines. A word line addressing the latch is provided through the transistors connected to the Bit Lines having shared body contact which permits reading and writing to the latch. During a write mode, the word line is connected to a potential which renders transistors connected to the complementary bit lines conductive, while the write bit connected to a potential which renders the remaining transistors nonconducting. During a read operation, one of the remaining transistors are rendered conductive, and the word line renders the set of transistors connected to the Bit Lines conductive so that the bit Lines are charged from the respective nodes of the latch.
摘要翻译：具有减小的表面积的静态RAM单元。静态RAM单元包括一对P沟道晶体管和作为双稳态锁存器连接的一对N沟道晶体管。锁存器的第一个公共源极连接连接到写入位端，并且锁存器的其余源极连接连接到互补位线。通过连接到具有共享体接触的位线的晶体管提供寻址锁存器的字线，其允许读取和写入锁存器。在写入模式期间，字线连接到使连接到互补位线的晶体管导通的电位，而写入位连接到使剩余晶体管不导通的电位。在读取操作期间，剩余晶体管中的一个导通，并且字线使连接到位线的晶体管组导通，使得位线从锁存器的相应节点充电。

130. 发明授权

US5959335A Device design for enhanced avalanche SOI CMOS 有权
标题翻译：增强型雪崩SOI CMOS器件设计
公开(公告)号：US5959335A
公开(公告)日：1999-09-28
申请号：US159307
申请日：1998-09-23
申请人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
发明人： Andres Bryant , William F. Clark , John J. Ellis-Monaghan , Edward P. Maciejewski , Edward J. Nowak , Wilbur D. Pricer , Minh H. Tong
IPC分类号： H01L27/06 , H01L21/8234 , H01L27/12 , H01L29/78 , H01L29/786 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L29/7841 , H01L27/1203
摘要： A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.
摘要翻译：用于SOI CMOS中的FET的器件设计，其被设计用于当FET导通时增强通过器件的电流的雪崩倍增，并且当FET关闭时去除体电荷。 FET具有电浮动体并且与衬底基本上电隔离。本发明提供了将FET的浮体耦合到FET的源极的高电阻路径，使得该电阻器使得该器件能够充当用于有源开关目的的浮动体并且作为待机模式中的接地体以减少漏电流。高电阻路径具有至少1MΩ的电阻，并且包括通过使用分离多晶硅工艺制造的多晶硅电阻器，其中掩埋接触掩模在第一多晶硅层中打开孔，以允许第二多晶硅层接触基板。

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