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121. 发明申请

US20080117237A1 LIQUID CRYSTAL DRIVING CIRCUIT AND LOAD DRIVING CIRCUIT 审中-公开
标题翻译：液晶驱动电路和负载驱动电路
公开(公告)号：US20080117237A1
公开(公告)日：2008-05-22
申请号：US12016511
申请日：2008-01-18
申请人： Tetsuya SAITO , Hironori Minamizaki , Tetsuro Itakura
发明人： Tetsuya SAITO , Hironori Minamizaki , Tetsuro Itakura
IPC分类号： G09G5/10 , H03B1/00
CPC分类号： G09G3/3696 , G09G3/2011 , G09G3/3688 , G09G2310/027 , G09G2330/021 , G09G2360/16
摘要： There is disclosed a liquid crystal driving circuit configured to supply an analog voltage in accordance with digital grayscale data to each of a plurality of signal lines, said circuit comprising: a reference voltage generation circuit configured to output analog reference voltages corresponding to each of said digital grayscale data; a plurality of buffer amplifiers configured to individually perform buffering of said respective analog reference voltages; a grayscale mode circuit configured to determine a grayscale number of said digital grayscale data based on a grayscale mode signal supplied from the outside; and an amplifier enable circuit configured to set each of said plurality of buffer amplifiers to an enable state or a disable state based on an output signal of said grayscale mode circuit.
摘要翻译：公开了一种液晶驱动电路，其被配置为将数字灰度数据的模拟电压提供给多条信号线中的每条信号线，所述电路包括：参考电压产生电路，被配置为输出对应于每个所述数字灰度数据; 多个缓冲放大器，被配置为单独地执行所述各个模拟参考电压的缓冲; 灰度模式电路，被配置为基于从外部提供的灰度模式信号来确定所述数字灰度数据的灰度数; 以及放大器使能电路，被配置为基于所述灰度级模式电路的输出信号将所述多个缓冲放大器中的每一个设置为使能状态或禁用状态。

122. 发明授权

US07123061B2 Frequency converter having low supply voltage 失效
标题翻译：变频器具有低电源电压
公开(公告)号：US07123061B2
公开(公告)日：2006-10-17
申请号：US11235264
申请日：2005-09-27
申请人： Toshiyuki Umeda , Shoji Otaka , Tetsuro Itakura
发明人： Toshiyuki Umeda , Shoji Otaka , Tetsuro Itakura
IPC分类号： H03B19/00
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D2200/0033 , H03D2200/0043 , H03D2200/0084
摘要： A frequency converter converts a first current signal having a first frequency into a second current signal having a second frequency different from the first frequency. The frequency converter includes an adder and a switching circuit. The adder adds the first current signal and a reference current signal to output a third current signal. The switching circuit passes only that portion of the third current signal larger in magnitude than a threshold current to output the second current signal.
摘要翻译：变频器将具有第一频率的第一电流信号转换成具有与第一频率不同的第二频率的第二电流信号。变频器包括加法器和开关电路。加法器将第一电流信号和参考电流信号相加以输出第三电流信号。开关电路仅通过第三电流信号的大于阈值电流的部分，以输出第二电流信号。

123. 发明申请

US20060221099A1 Image data processing apparatus and image data processing method 失效
标题翻译：图像数据处理装置和图像数据处理方法
公开(公告)号：US20060221099A1
公开(公告)日：2006-10-05
申请号：US11231762
申请日：2005-09-22
申请人： Haruhiko Okumura , Tetsuro Itakura , Hironori Minamizaki
发明人： Haruhiko Okumura , Tetsuro Itakura , Hironori Minamizaki
IPC分类号： G09G5/00
CPC分类号： G06F3/1415 , G09G3/2096 , G09G3/3688 , G09G5/006 , G09G5/008 , G09G2310/027 , G09G2330/06 , G09G2340/16 , G09G2370/045 , G09G2370/047
摘要： An image data processing apparatus includes: a data dividing unit dividing arithmetic image data into arithmetic pixel data corresponding to a signal line of a display device; an adder adding first data and second data; and a data delaying unit delaying the added data, wherein the first data is the divided arithmetic pixel data from the data dividing unit, and the second data is the delayed added arithmetic pixel data from the data delaying unit.
摘要翻译：图像数据处理装置包括：数据划分单元，将运算图像数据分割成与显示装置的信号线对应的算术像素数据; 加法器，其添加第一数据和第二数据; 以及数据延迟单元延迟所添加的数据，其中所述第一数据是来自所述数据分割单元的分割的运算像素数据，并且所述第二数据是来自所述数据延迟单元的延迟加法运算像素数据。

124. 发明授权

US06977541B2 Variable time constant circuit and filter circuit using the same 失效
标题翻译：可变时间常数电路和滤波电路使用相同
公开(公告)号：US06977541B2
公开(公告)日：2005-12-20
申请号：US10743949
申请日：2003-12-24
申请人： Daisuke Kurose , Tetsuro Itakura , Rui Ito
发明人： Daisuke Kurose , Tetsuro Itakura , Rui Ito
IPC分类号： H03F3/45 , G06G7/18 , H03F1/00 , H03F3/345 , H03H11/04 , H03H11/12 , H03H11/24 , H03H11/32 , H04B1/10
CPC分类号： H03H11/32 , H03F3/345 , H03F3/45475 , H03F2203/45511 , H03F2203/45512 , H03F2203/45592 , H03F2203/45652 , H03H11/1291 , H03H11/245
摘要： A variable time constant circuit includes an inverting amplifier which has an amplifier input terminal and an amplifier output terminal connected to a signal output terminal and inverts a signal inputted to the amplifier input terminal, a first and a second resistor which are connected in series between the signal input terminal and the amplifier input terminal, a capacitor connected between the amplifier input terminal and the amplifier output terminal, a field effect transistor including a gate terminal connected to a junction point of the first and second resistors, a source terminal kept at a constant potential, and a drain terminal connected to the amplifier input terminal, the transistor flowing a current through the drain terminal according to a voltage between the gate terminal and the source terminal, and a control circuit which controls a voltage-current conversion ratio of the transistor according to a time constant control signal.
摘要翻译：可变时间常数电路包括反相放大器，其具有放大器输入端和连接到信号输出端的放大器输出端，并且反相输入到放大器输入端的信号，第一和第二电阻串联在第信号输入端子和放大器输入端子，连接在放大器输入端子和放大器输出端子之间的电容器，场效应晶体管，其包括连接到第一和第二电阻器的接合点的栅极端子，源极端子保持恒定电位和连接到放大器输入端子的漏极端子，晶体管根据栅极端子和源极端子之间的电压流过漏极端子，以及控制电路，其控制晶体管的电压 - 电流转换比根据时间常数控制信号。

125. 发明授权

US06664941B2 Amplifier circuit and liquid-crystal display unit using the same 失效
标题翻译：放大电路和液晶显示单元使用相同
公开(公告)号：US06664941B2
公开(公告)日：2003-12-16
申请号：US10189452
申请日：2002-07-08
申请人： Tetsuro Itakura , Takeshi Shima
发明人： Tetsuro Itakura , Takeshi Shima
IPC分类号： G09G336
CPC分类号： H03F3/303 , G09G3/3688 , H03F3/3023
摘要： An amplifier circuit including an input stage and an output stage which are cascade-connected between a signal input terminal to which an input signal is input and a signal output terminal to which a capacitive load is connected, and which includes at least an input amplification stage and an output amplification stage, and a resistor circuit including at least a resistor inserted between the output terminal of the output amplification stage and the signal output terminal.
摘要翻译：一种放大器电路，包括输入级和输出级，级联连接在输入输入信号的信号输入端与连接有电容性负载的信号输出端之间，并且至少包括输入放大级和输出放大级，以及至少包括插入在输出放大级的输出端子与信号输出端子之间的电阻器的电阻电路。

126. 发明授权

US06411162B1 Amplifier device and LCD device 有权
公开(公告)号：US06411162B1
公开(公告)日：2002-06-25
申请号：US09813958
申请日：2001-03-22
申请人： Hironori Minamizaki , Tetsuro Itakura , Tetsuya Saito
发明人： Hironori Minamizaki , Tetsuro Itakura , Tetsuya Saito
IPC分类号： H03F345
摘要： In an amplifier device, a negative output voltage (−) of a differential amplifier stage corresponding to an input signal voltage (Vin) is supplied to the gate of Output transistor M25 for charging electrical charges to Capacitive load (80). A current corresponding to a positive output voltage (+) of the differential amplifier stage is supplied to Node (A) through which the gate of Output transistor M26 for discharging electrical charges from Capacitive load (80) is connected to Constant current source (4). This current becomes a value (Iy+&Dgr;I) according to the voltage (Vin). By changing the gate voltage of Output transistor M26, it enters ON, and the electrical charges are discharged as a current I3 from Capacitive load (80). The voltage (Vin) is converted to a current by Voltage-current converter (1), and Current-voltage converter (2) then converts this current to a voltage. It is thereby possible to increase the driving ability of Output transistor M26 and to perform a response operation at high speed with low power consumption only by changing the current corresponding to the positive output voltage (+) of the differential pair.

127. 发明授权

US5280199A Differential input circuit and operational amplifier with wide common mode input voltage range 失效
标题翻译：差分输入电路和运算放大器具有宽共模输入电压范围
公开(公告)号：US5280199A
公开(公告)日：1994-01-18
申请号：US882535
申请日：1992-05-13
申请人： Tetsuro Itakura
发明人： Tetsuro Itakura
IPC分类号： H03F3/45 , H03K5/22
CPC分类号： H03F3/45183 , H03F3/45654 , H03F3/45708 , H03F3/45713 , H03F2200/18 , H03F2203/45002 , H03F2203/45018 , H03F2203/45031 , H03F2203/45074 , H03F2203/45212 , H03F2203/45318
摘要： A differential input circuit capable of realizing a wide common mode input range, without using a current summing circuit, in which the total output current is independent of the common mode input voltage level. The circuit includes: a first differential pair formed by two transistors connected to a current source; a second differential pair connected to the current source in parallel to the first differential pair, including two transistor combinations, each of which is formed by two transistors of mutually complementary conductivity/polarity types having source/emitter electrodes connected to each other; in which bias voltages are applied to gate/base electrodes of one of transistors of each transistor combination in the second differential pair which has an identical conductivity/polarity type as the transistors of the first differential pair. The outputs are connected with the first and second differential pairs such that the first and second differential pairs have the same output current direction. Differential and operational amplifier configurations using this differential input circuit are also disclosed.
摘要翻译：一种差分输入电路，其能够实现宽共模输入范围，而不使用电流求和电路，其中总输出电流独立于共模输入电压电平。该电路包括：由连接到电流源的两个晶体管形成的第一差分对; 包括两个晶体管组合的第二差分对，其与电流源并联连接到第一差分对，每个晶体管组合由具有彼此连接的源/发射极的相互互补的导电/极性类型的两个晶体管形成; 其中偏置电压施加到具有与第一差分对的晶体管相同的导电/极性类型的第二差分对中的每个晶体管组合的晶体管之一的栅/基极。输出与第一和第二差分对连接，使得第一和第二差分对具有相同的输出电流方向。还公开了使用该差分输入电路的差分和运算放大器配置。

128. 发明授权

US4709408A Phased lock loop synchronous detecting system with an automatic frequency tuning circuit 失效
标题翻译：具有自动频率调谐电路的相控锁环同步检测系统
公开(公告)号：US4709408A
公开(公告)日：1987-11-24
申请号：US760984
申请日：1985-07-31
申请人： Tetsuro Itakura , Yoshitaka Kasagi , Mikio Koyama , Chikashi Nakagawara
发明人： Tetsuro Itakura , Yoshitaka Kasagi , Mikio Koyama , Chikashi Nakagawara
IPC分类号： H04N5/455 , H03J7/04 , H04N5/04 , H04N5/50 , H04B1/16
CPC分类号： H04N5/4446 , H03J7/04 , H04N5/50
摘要： A circuit for processing an intermediate frequency signal comprises a limiter connected to receive the intermediate frequency signal to generate a carrier component of the intermediate frequency signal as an output, a phase locked loop circuit connected to receive one of the intermediate frequency signal and the carrier component from the limiter to generate an output signal which is phase-locked onto the carrier component of the intermediate frequency signal, a synchronous detector for synchronously detecting the intermediate frequency signal depended on the output signal from the phase locked loop circuit, and an automatic frequency circuit connected to receive the carrier component from the limiter and the output signal from the phase locked loop circuit to generate an output signal, as an automatic frequency tuning signal, in response to a frequency difference therebetween.
摘要翻译：一种用于处理中频信号的电路包括限幅器，其连接以接收中频信号以产生作为输出的中频信号的载波分量;锁相环电路，被连接以接收中频信号和载波分量之一从限幅器产生相位锁定在中频信号的载波分量上的输出信号，同步检波器，用于根据来自锁相环电路的输出信号同步检测中频信号;以及自动频率电路连接以从限幅器接收载波分量和来自锁相环电路的输出信号，以响应于它们之间的频率差而产生作为自动频率调谐信号的输出信号。

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