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121. 发明授权

US06538653B1 Graphic processing system for displaying characters and pictures at high speed 失效
公开(公告)号：US06538653B1
公开(公告)日：2003-03-25
申请号：US08625241
申请日：1996-04-01
申请人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
发明人： Koyo Katsura , Shigeru Matsuo , Shigeaki Yoshida , Hiroshi Takeda , Hisashi Kaziwara
IPC分类号： G06T340
CPC分类号： G09G5/393 , G09G5/22 , G09G5/26 , G09G5/363
摘要： A graphic processing system has a processor for managing a display area and a character font area both included within an address space. From coded information indicative of a character transferred through a data bus of the system, the processor generates an address at which a character font pattern of the corresponding character has been stored and transfers that character font pattern to a predetermined position on the display area. The graphic processing system realizes high speed development of fonts.

122. 发明授权

US06518235B1 Methods for improving brain function using leptin or analogs thereof 失效
标题翻译：使用瘦素或其类似物改善脑功能的方法
公开(公告)号：US06518235B1
公开(公告)日：2003-02-11
申请号：US09200919
申请日：1998-11-30
申请人： Yutaka Oomura , Nobuaki Hori , Takemasa Shiraishi , Kazuo Sasaki , Hiroshi Takeda , Minoru Tsuji , Teruhiko Matsumiya
发明人： Yutaka Oomura , Nobuaki Hori , Takemasa Shiraishi , Kazuo Sasaki , Hiroshi Takeda , Minoru Tsuji , Teruhiko Matsumiya
IPC分类号： A01N3718
CPC分类号： C07K14/5759 , A61K38/2264
摘要： The present invention is to provide a drug for improvement of brain function which is effective to prevent from or to cure dementia such as Alzheimer's disease. The drug for improvement of brain function of this invention comprises leptin of mammals as an effective component wherefore has a superior effect in improvement of learning and memory.
摘要翻译：本发明提供一种改善脑功能的药物，其有效地防止或治愈诸如阿尔茨海默病的痴呆症。用于改善本发明的脑功能的药物包括哺乳动物的瘦素作为有效成分，因此在改善学习和记忆方面具有优异的效果。

123. 发明授权

US06247073B1 Memory outputting both data and timing signal with output data and timing signal being aligned with each other 有权
标题翻译：存储器输出数据和定时信号，输出数据和定时信号彼此对准
公开(公告)号：US06247073B1
公开(公告)日：2001-06-12
申请号：US09400999
申请日：1999-09-21
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G06F1200
CPC分类号： G11C7/1027 , G06F13/1689 , G11C7/22
摘要： A memory 1 performs its internal operation in response to access requests (200, 201 and 202) of a CPU 2 in synchronism with the oscillated output of a self-excited oscillator 102 incorporated therein and according to said access requests, and outputs a response request 103 for said access requests to said CPU in synchronism with its internal operation. The CPU performs the access requests for the memory, and fetches data from the outside or outputs the data to the outside in response to and in synchronism with the response request 103 from the accessed memory and according to the kinds of said access requests.
摘要翻译：存储器1响应于CPU 2的接收请求（200,201和202）与其中并入的自激振荡器102的振荡输出同步并且根据所述访问请求执行其内部操作，并且输出响应请求 103，用于与其内部操作同步地对所述CPU的所述访问请求。 CPU执行对存储器的访问请求，并且从外部获取数据或者响应于来自所访问的存储器的响应请求103并根据所述访问请求的种类而将数据输出到外部。

124. 发明授权

US5610622A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US5610622A
公开(公告)日：1997-03-11
申请号：US309413
申请日：1994-09-20
申请人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
发明人： Hiroshi Takeda , Shigeaki Yoshida , Koyo Katsura
IPC分类号： G09G5/18 , G09G5/12 , G09G1/08
CPC分类号： G09G5/12
摘要： A CRT (cathode ray tube) controller for controlling one CRT device in an interlace mode has a synchronizing circuit of bi-directional construction, in order to make possible synchronous operation of the CRT controller with other circuits (other CRT controllers or a TV system). When the CRTC is used as a master circuit of a CRT display system, a synchronizing signal is derived from the synchronizing circuit in synchronization on with a count signal of a vertical scanning counter and an output of an interlace controller of the CRTC, and is supplied to a synchronizing terminal of the other CRTCs. Scanning counters and a flip-flop for controlling an interlace operation of the other CRTCs are reset to their initial state in synchronization with the synchronizing signal. When the CRTC is used as a slave circuit, scanning counters and a flip-flop of the CRTC are reset to their initial state in synchronization with the external synchronizing signal.
摘要翻译：用于以隔行模式控制一个CRT器件的CRT（阴极射线管）控制器具有双向结构的同步电路，以便使CRT控制器与其他电路（其它CRT控制器或TV系统）可以同步操作，。当CRTC用作CRT显示系统的主电路时，根据垂直扫描计数器的计数信号和CRTC的隔行控制器的输出，同步信号从同步电路得到，并被提供到其他CRTC的同步终端。用于控制其他CRTC的隔行扫描的扫描计数器和触发器与同步信号同步地被复位到其初始状态。当CRTC用作从电路时，与外部同步信号同步，将扫描计数器和CRTC的触发器复位到初始状态。

125. 发明授权

US5511178A Cache control system equipped with a loop lock indicator for indicating the presence and/or absence of an instruction in a feedback loop section 失效
标题翻译：缓存控制系统配备有用于指示反馈回路部分中存在和/或不存在指令的循环锁定指示器
公开(公告)号：US5511178A
公开(公告)日：1996-04-23
申请号：US156301
申请日：1993-11-23
申请人： Hiroshi Takeda , Shigezumi Matsui
发明人： Hiroshi Takeda , Shigezumi Matsui
IPC分类号： G06F9/38 , G06F9/45 , G06F12/08 , G06F12/12 , G06F12/02
CPC分类号： G06F9/381 , G06F12/0862 , G06F2212/6028
摘要： In a cache memory 20, there exist a plurality of cache lines 201, each of which is equipped with a loop lock L for indicating that an instruction is present in a feedback loop section. The states of the loop locks L are dynamically changed according to the executed state of a program. At the time of excluding the cache lines for a prefetch, the instruction string in the loop is held in the cache memory 20 till the program control transfers to the outside of the loop.
摘要翻译：在高速缓冲存储器20中，存在多个高速缓存线201，每条高速缓存线201配备有用于指示反馈回路部分中存在指令的回路锁L。循环锁L的状态根据程序的执行状态而动态变化。在排除用于预取的高速缓存行时，循环中的指令串被保存在高速缓冲存储器20中，直到程序控制转移到循环的外部。

126. 发明授权

US5452469A Command performing order change over system based on information contained in executed command in a data processor 失效
标题翻译：基于在数据处理器中执行的命令中包含的信息，执行系统的命令改变
公开(公告)号：US5452469A
公开(公告)日：1995-09-19
申请号：US164688
申请日：1993-12-09
申请人： Takashi Sone , Hiroshi Takeda , Jun Satoh , Shigeru Matsuo
发明人： Takashi Sone , Hiroshi Takeda , Jun Satoh , Shigeru Matsuo
IPC分类号： G06F13/12 , G06F9/26 , G06F9/38 , G06F11/22 , G06F11/28 , G06F11/36 , G06F9/24 , G06F9/30 , G06F9/445 , G06F13/16
CPC分类号： G06F11/3648 , G06F9/265 , G06F9/3877
摘要： A slave controller formed on a single semiconductor substrate executes a built in control algorithm in response to a command supplied from a master controller. Upon completion of command execution, the controls respond to predetermined information contained within the command by branching internal control operation in accordance with the new command. The controls then suspend a series of operations for executing the new command upon detection of the branch condition. Once the internal state has been changed over, the slave controller sends an instruction to the master controller.
摘要翻译：形成在单个半导体衬底上的从控制器响应于从主控制器提供的命令执行内置的控制算法。命令执行完成后，通过根据新命令分支内部控制操作来控制命令中包含的预定信息。然后，控制器在检测到分支条件后暂停执行新命令的一系列操作。一旦内部状态已经改变，从控制器向主控制器发送指令。

127. 发明授权

US5341471A Controller for accessing an image data memory based on a state of a hard copy printer 失效
标题翻译：控制器，用于基于硬拷贝打印机的状态访问图像数据存储器
公开(公告)号：US5341471A
公开(公告)日：1994-08-23
申请号：US961424
申请日：1992-10-15
申请人： Hideki Yamazaki , Hiroshi Takeda , Yoshikazu Yokota
发明人： Hideki Yamazaki , Hiroshi Takeda , Yoshikazu Yokota
IPC分类号： G06K15/02 , G06K15/12 , G06T1/60 , G06F15/62
CPC分类号： G06K15/02 , G06K15/128 , G06T1/60 , G06K2215/0011 , G06K2215/0017
摘要： An image memory controller having a first address signal generating unit generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generating unit generates a second address signal for refreshing the image memory and a third address signal generating unit generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second, and third address signals to the image memory.
摘要翻译：一种图像存储器控制器，具有第一地址信号产生单元，响应于表示打印机操作状态的状态信号产生第一地址信号。第一地址信号对应于图像存储器中的位置。第二地址信号产生单元生成用于刷新图像存储器的第二地址信号，第三地址信号生成单元生成用于重写存储在图像存储器中的数据的至少一部分的第三地址信号。地址信号选择器选择性地将第一，第二和第三地址信号中的任何一个传送到图像存储器。

128. 发明授权

US5262767A Display control device 失效
标题翻译：显示控制装置
公开(公告)号：US5262767A
公开(公告)日：1993-11-16
申请号：US727421
申请日：1991-07-09
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G06T11/80 , G09G5/393 , G09G1/16
CPC分类号： G09G5/393
摘要： A CRT controller having a drawing function includes designation means to designate a predetermined area of an external memory as a reference area for tiling, and a drawing processor which transmits a display pattern in the reference area designated by the designation means, to a drawing area of the external memory. Since the CRT controller of this construction permits the use of the external memory easy of enlarging the capacity thereof for a tiling pattern, it realizes the tiling processing with a complicated tiling pattern.
摘要翻译：具有绘图功能的CRT控制器包括指定装置，用于指定外部存储器的预定区域作为平铺的参考区域;以及绘图处理器，其将指定装置指定的参考区域中的显示图案发送到绘图区域外部存储器。由于这种结构的CRT控制器允许使用外部存储器容易地扩大其对于平铺图案的容量，所以它以复杂的平铺图案实现了平铺处理。

129. 发明授权

US5067097A Image memory controller 失效
标题翻译：图像存储控制器
公开(公告)号：US5067097A
公开(公告)日：1991-11-19
申请号：US494874
申请日：1990-03-08
申请人： Hideki Yamazaki , Hiroshi Takeda , Yoshikazu Yokota
发明人： Hideki Yamazaki , Hiroshi Takeda , Yoshikazu Yokota
IPC分类号： G06F3/12 , G06F3/153 , G06K15/02 , G06K15/12 , G06T1/60 , H04N5/76
CPC分类号： G06K15/128 , G06K15/02 , G06T1/60 , G06K2215/0011 , G06K2215/0017
摘要： An image memory controller having a first address signal generator for generating a first address signal in response to a state signal representing the operational state of a printer. The first address signal corresponds to a location in an image memory. A second address signal generator generates a second address signal for refreshing the image memory and a third address signal generation means generates a third address signal used for rewriting at least part of data stored in the image memory. An address signal selector selectively delivers any of the first, second and third address signals to the image memory.
摘要翻译：一种图像存储器控制器，具有第一地址信号发生器，用于响应于表示打印机的操作状态的状态信号产生第一地址信号。第一地址信号对应于图像存储器中的位置。第二地址信号发生器产生用于刷新图像存储器的第二地址信号，第三地址信号产生装置产生用于重写存储在图像存储器中的数据的至少一部分的第三地址信号。地址信号选择器选择性地将第一，第二和第三地址信号中的任何一个传送到图像存储器。

130. 发明授权

US5043717A Display control device 失效
公开(公告)号：US5043717A
公开(公告)日：1991-08-27
申请号：US448831
申请日：1989-12-12
申请人： Hiroshi Takeda
发明人： Hiroshi Takeda
IPC分类号： G09G5/24 , G06T11/20 , G09G1/14 , G09G5/36 , G09G5/393
CPC分类号： G09G5/393
摘要： A CRT controller having a drawing function includes designation means to designate a predetermined area of an external memory as a reference area for tiling, and a drawing processor which transmits a display pattern in the reference area designated by the designation means, to a drawing area of the external memory. Since the CRT controller of this construction permits the use of the external memory easy of enlarging the capacity thereof for a tiling pattern, it realizes the tiling processing with a complicated tiling pattern.

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