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121. 发明授权

US07603523B2 Method and apparatus for filtering snoop requests in a point-to-point interconnect architecture 失效
标题翻译：用于在点对点互连架构中过滤窥探请求的方法和装置
公开(公告)号：US07603523B2
公开(公告)日：2009-10-13
申请号：US12035085
申请日：2008-02-21
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
IPC分类号： G06F12/08 , G06F13/00
CPC分类号： G06F12/0831 , G06F12/084 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于从多处理器计算环境中的专用存储器写入源接收窥探请求。每个存储器写入源以点对点互连方式直接连接到与所有其他处理单元相关联的所有其他窥探滤波器设备的专用输入端口。每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，该多个专用输入端口适于同时滤除从相应专用存储器写入源接收到的窥探请求，并将这些请求的子集转发到其相关联的处理单元。

122. 发明申请

US20090006769A1 PROGRAMMABLE PARTITIONING FOR HIGH-PERFORMANCE COHERENCE DOMAINS IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：用于多处理器系统中高性能协调域的可编程分区
公开(公告)号：US20090006769A1
公开(公告)日：2009-01-01
申请号：US11768532
申请日：2007-06-26
申请人： Matthias A. Blumrich , Valentina Salapura
发明人： Matthias A. Blumrich , Valentina Salapura
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A multiprocessor computing system and a method of logically partitioning a multiprocessor computing system are disclosed. The multiprocessor computing system comprises a multitude of processing units, and a multitude of snoop units. Each of the processing units includes a local cache, and the snoop units are provided for supporting cache coherency in the multiprocessor system. Each of the snoop units is connected to a respective one of the processing units and to all of the other snoop units. The multiprocessor computing system further includes a partitioning system for using the snoop units to partition the multitude of processing units into a plurality of independent, memory-consistent, adjustable-size processing groups. Preferably, when the processor units are partitioned into these processing groups, the partitioning system also configures the snoop units to maintain cache coherency within each of said groups.
摘要翻译：公开了一种多处理器计算系统和逻辑划分多处理器计算系统的方法。多处理器计算系统包括多个处理单元和多个窥探单元。每个处理单元包括本地高速缓存，并且提供窥探单元用于在多处理器系统中支持高速缓存一致性。每个窥探单元连接到相应的一个处理单元和所有其他窥探单元。多处理器计算系统还包括用于使用窥探单元将多个处理单元划分成多个独立的，存储器一致的可调整大小的处理组的分区系统。优选地，当处理器单元被划分成这些处理组时，分区系统还配置窥探单元以维持每个所述组内的高速缓存一致性。

123. 发明申请

US20090006546A1 MULTIPLE NODE REMOTE MESSAGING 有权
标题翻译：多个节点远程消息传递
公开(公告)号：US20090006546A1
公开(公告)日：2009-01-01
申请号：US11768784
申请日：2007-06-26
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Burkhard Steinmacher-Burow , Pavlos Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Martin Ohmacht , Valentina Salapura , Burkhard Steinmacher-Burow , Pavlos Vranas
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A method for passing remote messages in a parallel computer system formed as a network of interconnected compute nodes includes that a first compute node (A) sends a single remote message to a remote second compute node (B) in order to control the remote second compute node (B) to send at least one remote message. The method includes various steps including controlling a DMA engine at first compute node (A) to prepare the single remote message to include a first message descriptor and at least one remote message descriptor for controlling the remote second compute node (B) to send at least one remote message, including putting the first message descriptor into an injection FIFO at the first compute node (A) and sending the single remote message and the at least one remote message descriptor to the second compute node (B).
摘要翻译：在形成为互连的计算节点的网络的并行计算机系统中传递远程消息的方法包括：第一计算节点（A）将单个远程消息发送到远程第二计算节点（B），以便控制远程第二计算节点（B）发送至少一个远程消息。该方法包括各种步骤，包括在第一计算节点（A）处控制DMA引擎以准备单个远程消息以包括第一消息描述符和至少一个远程消息描述符，用于控制远程第二计算节点（B）至少发送一个远程消息，包括将第一消息描述符放在第一计算节点（A）的注入FIFO中，并将单个远程消息和至少一个远程消息描述符发送到第二计算节点（B）。

124. 发明申请

US20080192749A1 METHOD AND SYSTEM OF EFFICIENT PACKET REORDERING 失效
标题翻译：高效包装的方法与系统
公开(公告)号：US20080192749A1
公开(公告)日：2008-08-14
申请号：US12105968
申请日：2008-04-18
申请人： Christos J. GEORGIOU , Valentina Salapura
发明人： Christos J. GEORGIOU , Valentina Salapura
IPC分类号： H04L12/56
CPC分类号： H04L47/10 , H04L47/34
摘要： A method and system is provided to efficiently order packets received over a network. The method detects breaks in sequences for one or more packet flows by detecting out-of-sequence packets and enters the segment of sequential packets into a separate memory area, such as a linked list, for a particular flow. A transmission queue and reorder table is used to record the beginning sequence number for each segment. The transmission queue is consulted to locate the segment beginning with the lowest packet sequence number for a flow. The packets associated with the segment are transmitted in order. The transmission queue is then repeatedly searched for the next lowest packet sequence number for transmission of the associated packet chain until the transmission queue is emptied.
摘要翻译：提供了一种方法和系统来有效地排序通过网络接收的分组。该方法通过检测失序分组来检测一个或多个分组流的序列中断，并且将顺序分组的分段进入用于特定流的单独的存储区域，例如链表。传输队列和重排序表用于记录每个段的起始序列号。参考传输队列以定位从流的最低分组序列号开始的分段。与段相关联的分组按顺序传输。然后，重复地搜索传输队列用于相关联的分组链的传输的下一个最低分组序列号，直到传输队列被清空。

125. 发明授权

US07386685B2 Method and apparatus for filtering snoop requests using multiple snoop caches 有权
标题翻译：用于使用多个监听高速缓存来过滤窥探请求的方法和装置
公开(公告)号：US07386685B2
公开(公告)日：2008-06-10
申请号：US11093154
申请日：2005-03-29
申请人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
发明人： Matthias A. Blumrich , Alan G. Gara , Valentina Salapura
IPC分类号： G06F13/28 , G06F12/00
CPC分类号： G06F12/0831 , G06F12/0822 , G06F2212/507 , Y02D10/13
摘要： A method and apparatus for implementing a snoop filter unit associated with a single processor in a multiprocessor system. The snoop filter unit has a plurality of ports, each port receiving snoop requests from exactly one dedicated source. Associated with each port is a snoop cache filter that processes each snoop cache request and records addresses of the most recent snoop requests for exactly one source. The snoop cache filter uses vector encoding to record the occurrence of snoop requests for a sequence of consecutive cache lines. All addresses of snoop requests are added to the snoop cache unless a received snoop cache request matches an entry present in the associated snoop cache, in which case the snoop request is discarded. Otherwise, the associated snoop cache request is enqueued for forwarding to the single processor. Information from all snoop cache filters assigned to all ports in the snoop filter unit are removed in the case that data corresponding to any one of the memory addresses contained in snoop cache filter is loaded in the cache hierarchy of the processor the snoop cache filter is assigned to.
摘要翻译：一种用于在多处理器系统中实现与单个处理器相关联的窥探滤波器单元的方法和装置。监听过滤器单元具有多个端口，每个端口接收来自正好一个专用源的窥探请求。与每个端口相关联的是一个侦听缓存过滤器，用于处理每个侦听缓存请求，并记录最近一次侦听请求的地址。监听高速缓存过滤器使用向量编码来记录连续高速缓存行序列的窥探请求的发生。侦听请求的所有地址都将添加到侦听缓存中，除非接收到的侦听缓存请求与相关侦听缓存中存在的条目匹配，在这种情况下，侦听请求将被丢弃。否则，相关联的侦听缓存请求被排入队列以转发到单个处理器。在分配给窥探过滤器单元中的所有端口的所有侦听缓存过滤器中的信息将被删除，因为与侦听高速缓存过滤器中包含的任何一个存储器地址相对应的数据被加载到处理器的高速缓存层次结构中，该侦听缓存过滤器被分配至。

126. 发明申请

US20080133845A1 METHOD AND APPARATUS FOR FILTERING SNOOP REQUESTS IN A POINT-TO-POINT INTERCONNECT ARCHITECTURE 失效
标题翻译：在点对点互连架构中过滤SNOOP要求的方法和装置
公开(公告)号：US20080133845A1
公开(公告)日：2008-06-05
申请号：US12035085
申请日：2008-02-21
申请人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
发明人： Matthias A. Blumrich , Dong Chen , Alan G. Gara , Mark E. Giampapa , Philip Heidelberger , Dirk I. Hoenicke , Martin Ohmacht , Valentina Salapura , Pavlos M. Vranas
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/084 , Y02D10/13
摘要： A method and apparatus for supporting cache coherency in a multiprocessor computing environment having multiple processing units, each processing unit having one or more local cache memories associated and operatively connected therewith. The method comprises providing a snoop filter device associated with each processing unit, each snoop filter device having a plurality of dedicated input ports for receiving snoop requests from dedicated memory writing sources in the multiprocessor computing environment. Each of the memory writing sources is directly connected to the dedicated input ports of all other snoop filter devices associated with all other processing units in a point-to-point interconnect fashion. Each snoop filter device includes a plurality of parallel operating port snoop filters in correspondence with the plurality of dedicated input ports that are adapted to concurrently filter snoop requests received from respective dedicated memory writing sources and forward a subset of those requests to its associated processing unit.
摘要翻译：一种用于在具有多个处理单元的多处理器计算环境中支持高速缓存一致性的方法和装置，每个处理单元具有与其相关联并与之可操作地相连的一个或多个本地高速缓冲存储器。该方法包括提供与每个处理单元相关联的窥探过滤器设备，每个窥探过滤器设备具有多个专用输入端口，用于在多处理器计算环境中从专用存储器写入源接收窥探请求。每个存储器写入源以点对点互连方式直接连接到与所有其他处理单元相关联的所有其他窥探滤波器设备的专用输入端口。每个窥探过滤器装置包括与多个专用输入端口相对应的多个并行操作端口窥探滤波器，该多个专用输入端口适于同时滤除从相应专用存储器写入源接收到的窥探请求，并将这些请求的子集转发到其相关联的处理单元。

127. 发明申请

US20080043897A1 Low latency counter event indication 有权
公开(公告)号：US20080043897A1
公开(公告)日：2008-02-21
申请号：US11507308
申请日：2006-08-21
申请人： Alan G. Gara , Valentina Salapura
发明人： Alan G. Gara , Valentina Salapura
IPC分类号： G06M3/02
CPC分类号： H03K23/54
摘要： A hybrid counter array device for counting events with interrupt indication includes a first counter portion comprising N counter devices, each for counting signals representing event occurrences and providing a first count value representing lower order bits. An overflow bit device associated with each respective counter device is additionally set in response to an overflow condition. The hybrid counter array includes a second counter portion comprising a memory array device having N addressable memory locations in correspondence with the N counter devices, each addressable memory location for storing a second count value representing higher order bits. An operatively coupled control device monitors each associated overflow bit device and initiates incrementing a second count value stored at a corresponding memory location in response to a respective overflow bit being set. The incremented second count value is compared to an interrupt threshold value stored in a threshold register, and, when the second counter value is equal to the interrupt threshold value, a corresponding “interrupt arm” bit is set to enable a fast interrupt indication. On a subsequent roll-over of the lower bits of that counter, the interrupt will be fired.

128. 发明申请

US20050008011A1 METHOD AND SYSTEM OF DATA TRANSFER FOR EFFICIENT MEMORY UTILIZATION 失效
标题翻译：数据传输的方法和系统有效的记忆利用
公开(公告)号：US20050008011A1
公开(公告)日：2005-01-13
申请号：US10604295
申请日：2003-07-09
申请人： Christos Georgiou , Valentina Salapura
发明人： Christos Georgiou , Valentina Salapura
IPC分类号： H04L12/56
CPC分类号： H04L49/9078 , H04L49/90 , H04L49/901 , H04L49/9021 , H04L49/9052
摘要： A method and system is provided to efficiently manage memory in a network device that receives packets of variable size. The memory is allocated into portions whereby each portion, comprising multiple equally-sized buffers, receives packets of a particular size. One portion is used for smaller packet sizes and another portion is for larger packet sizes, although other portions may be created. As packets are received at the network device, they are stored into the appropriate memory portion based on their size. The number of available buffers in each portion is monitored so that, when it falls below a threshold, buffers are reallocated to the other thereby increasing the overall memory efficiency.
摘要翻译：提供了一种方法和系统来有效地管理接收可变大小的分组的网络设备中的存储器。存储器被分配到部分，由此包括多个相等大小的缓冲器的每个部分接收特定大小的分组。一部分用于较小的分组大小，另一部分用于较大的分组大小，但可以创建其他部分。当在网络设备处接收到分组时，它们基于它们的大小被存储到适当的存储器部分中。监视每个部分中的可用缓冲器的数量，使得当其低于阈值时，缓冲器被重新分配到另一个，从而增加总体存储器效率。

129. 发明授权

US09697002B2 Computer instructions for activating and deactivating operands 有权
公开(公告)号：US09697002B2
公开(公告)日：2017-07-04
申请号：US13251458
申请日：2011-10-03
申请人： Michael K Gschwind , Valentina Salapura
发明人： Michael K Gschwind , Valentina Salapura
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3836 , G06F9/30076 , G06F9/3016 , G06F9/30185 , G06F9/3832 , G06F9/384 , G06F9/3859 , G06F9/3861
摘要： An instruction set architecture (ISA) includes instructions for selectively indicating last-use architected operands having values that will not be accessed again, wherein architected operands are made active or inactive after an instruction specified last-use by an instruction, wherein the architected operands are made active by performing a write operation to an inactive operand, wherein the activation/deactivation may be performed by the instruction having the last-use of the operand or another (prefix) instruction.

130. 发明授权

US09354874B2 Scalable decode-time instruction sequence optimization of dependent instructions 有权
公开(公告)号：US09354874B2
公开(公告)日：2016-05-31
申请号：US13251409
申请日：2011-10-03
申请人： Michael K. Gschwind , Valentina Salapura
发明人： Michael K. Gschwind , Valentina Salapura
IPC分类号： G06F9/38 , G06F9/30
CPC分类号： G06F9/3005 , G06F9/30127 , G06F9/3013 , G06F9/30167 , G06F9/3017 , G06F9/30181 , G06F9/3826 , G06F9/3834 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863
摘要： Producer-consumer instructions, comprising a first instruction and a second instruction in program order, are fetched requiring in-order execution, the second instruction is modified by the processor so that the first instruction and second instruction can be completed out-of-order, the modification comprising any one of extending an immediate field of the second instruction using immediate field information of the first instruction or providing a source location of the first instruction as an additional source location to source locations of the second instruction.

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