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121. 发明授权

US08329480B2 Test pattern for detecting piping in a memory array 有权
标题翻译：用于检测存储器阵列中管道的测试模式
公开(公告)号：US08329480B2
公开(公告)日：2012-12-11
申请号：US12892479
申请日：2010-09-28
申请人： Che-Lun Hung , Hsiang-Chou Liao , Tuung Luoh , Ling-Wu Yang
发明人： Che-Lun Hung , Hsiang-Chou Liao , Tuung Luoh , Ling-Wu Yang
IPC分类号： G01R31/26
CPC分类号： G11C29/56 , G11C29/006
摘要： A method of detecting manufacturing defects at a memory array may include disposing an active area of a first width in communication with a first conductive member of the memory array to define a grounded conductive member, disposing an isolation structure of a second width in communication with a second conductive member of the memory array to define a floating conductive member, and providing an alternating arrangement of floating and grounded conductive members including arranging a plurality of the grounded and floating conductive members adjacent to each other to define a sequence of alternating floating and grounded conductive members. A corresponding test device is also provided.
摘要翻译：检测存储器阵列中的制造缺陷的方法可以包括将与存储器阵列的第一导电构件连通的第一宽度的有源区域设置为限定接地导电构件，将与第二宽度的隔离结构存储器阵列的第二导电构件以限定浮动导电构件，以及提供浮动和接地导电构件的交替布置，包括布置彼此相邻的多个接地和浮动导电构件，以限定一系列交替的浮动和接地导电会员还提供了相应的测试装置。

122. 发明授权

US08288280B2 Conductor removal process 有权
标题翻译：导体去除过程
公开(公告)号：US08288280B2
公开(公告)日：2012-10-16
申请号：US11780024
申请日：2007-07-19
申请人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
发明人： Yung-Tai Hung , Chin-Tsan Yeh , Chin-Ta Su , Ling-Wu Yang , Tung-Han Chuang
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L21/3212 , H01L21/32105
摘要： A conductor removal process is described, which is applied to a substrate that has thereon a plurality of patterns and a blanket conductor layer covering the patterns. An upper portion of the blanket conductor layer entirely over the patterns is oxidized to form a dielectric layer. A CMP step is performed to remove the dielectric layer and a portion of the remaining conductor layer in turn and thereby expose the patterns.
摘要翻译：描述了导体去除工艺，其应用于其上具有多个图案的基板和覆盖图案的覆盖层导体层。橡皮布导体层的整个图案上方的上部被氧化以形成电介质层。执行CMP步骤以依次去除电介质层和剩余导体层的一部分，从而暴露图案。

123. 发明申请

US20120122296A1 METHODOLOGY FOR WORDLINE SHORT REDUCTION 有权
标题翻译：短线减少的方法
公开(公告)号：US20120122296A1
公开(公告)日：2012-05-17
申请号：US12947309
申请日：2010-11-16
申请人： Tuung LUOH , Ling-Wu YANG , Tahone YANG , Kuang-Chao CHEN
发明人： Tuung LUOH , Ling-Wu YANG , Tahone YANG , Kuang-Chao CHEN
IPC分类号： H01L21/28
CPC分类号： H01L27/11568 , H01L21/76224
摘要： The method of forming a wordline is provided in the present invention. The proposed method includes steps of: (a) providing a plurality of SASTIs with a plurality of first POLY cells deposited thereon; and (b) depositing a first fill-in material having a relatively high etching rate oxide-like material in the plurality of SASTIs and on each side wall of the plurality of first POLY cells.
摘要翻译：在本发明中提供了形成字线的方法。所提出的方法包括以下步骤：（a）向多个SASTI提供多个沉积在其上的第一POLY单元; 和（b）在所述多个SASTI中和所述多个第一POLY电池的每个侧壁上沉积具有相对高蚀刻速率氧化物样材料的第一填充材料。

124. 发明授权

US08106191B2 Synthetic multimerizing agents 失效
标题翻译：合成多聚化剂
公开(公告)号：US08106191B2
公开(公告)日：2012-01-31
申请号：US10461705
申请日：2003-06-13
申请人： Dennis A. Holt , Terence P. Keenan , Tao Guo , Edgardo Laborde , Wu Yang
发明人： Dennis A. Holt , Terence P. Keenan , Tao Guo , Edgardo Laborde , Wu Yang
IPC分类号： C07D413/00 , C07D211/00 , C07D409/00 , C07D207/00 , C07D205/00 , C07F7/02
CPC分类号： C07D401/14 , C07D207/16 , C07D211/60 , C07D401/12 , C07D405/12
摘要： New compounds are disclosed for multimerizing immunophilins and proteins containing immunophilin or immunophilin-related domains. The compounds are of the formula M-L-Q where M is a synthetic ligand for an FKBP protein.
摘要翻译：公开了用于多聚化免疫亲和素和含有免疫亲和素相关结构域的蛋白质的新化合物。该化合物具有式M-L-Q，其中M是FKBP蛋白质的合成配体。

126. 发明申请

US20100178758A1 METHODS FOR FABRICATING DIELECTRIC LAYER AND NON-VOLATILE MEMORY 审中-公开
标题翻译：用于制造介电层和非易失性存储器的方法
公开(公告)号：US20100178758A1
公开(公告)日：2010-07-15
申请号：US12354602
申请日：2009-01-15
申请人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
发明人： Jeng-Hwa Liao , Jung-Yu Hsieh , Ling-Wu Yang
IPC分类号： H01L21/443 , H01L21/28
CPC分类号： H01L21/28202 , H01L21/0214 , H01L21/02211 , H01L21/02271 , H01L21/3145 , H01L29/40117
摘要： The method for fabricating the dielectric layer of the present invention is described as follows. A substrate is provided in a chamber, wherein the chamber is a single-wafer LPCVD chamber. A silicon source gas, an oxidation source gas and a nitridation source gas are then introduced into the chamber, wherein a volumetric flow rate ratio of the oxidation source gas to a total amount of the oxidation source gas and the nitridation source gas is varied within a range of 0.0245 to 0.375. Afterwards, the dielectric layer with a dielectric constant within a range of 4.8 to 7.6 is formed on the substrate.
摘要翻译：本发明的电介质层的制造方法如下所述。衬底设置在腔室中，其中腔室是单晶片LPCVD室。然后将硅源气体，氧化源气体和氮化源气体引入室中，其中氧化源气体与氧化源气体和氮化源气体的总量的体积流量比在范围为0.0245至0.375。之后，在基板上形成介电常数为4.8〜7.6的介质层。

127. 发明授权

US07652023B2 Heterocyclic CETP inhibitors 有权
公开(公告)号：US07652023B2
公开(公告)日：2010-01-26
申请号：US11560388
申请日：2006-11-16
申请人： Yufeng Wang , Wu Yang
发明人： Yufeng Wang , Wu Yang
IPC分类号： A61K31/506 , A61K31/4745 , A61K31/4439 , C07D403/02
CPC分类号： C07D417/12 , C07D249/08 , C07D277/42 , C07D401/12 , C07D403/12 , C07D471/04 , C07D491/04
摘要： Compounds of formula Ia and Ib wherein A, B, C and R1 are described herein.

128. 发明授权

US07625819B2 Interconnection process 有权
标题翻译：互连过程
公开(公告)号：US07625819B2
公开(公告)日：2009-12-01
申请号：US11806541
申请日：2007-06-01
申请人： Tuung Luoh , Ling-Wu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
发明人： Tuung Luoh , Ling-Wu Yang , Chin-Ta Su , Ta-Hung Yang , Kuang-Chao Chen
IPC分类号： H01L21/44 , H01L21/4763
CPC分类号： H01L21/76814 , H01L21/28518 , H01L21/76828
摘要： An interconnection process is provided. The process includes the following steps. Firstly, a semiconductor base having at least a electrical conductive region is provided. Next, a dielectric layer with a contact hole is formed to cover the semiconductor base, wherein the contact hole exposes part of the electrical conductive region. Then, a thermal process is performed on the semiconductor base covered with the dielectric layer. Lastly, a conductive layer is formed on the dielectric layer, wherein the conductive layer is electrically connected to the electrical conductive region through the contact hole.
摘要翻译：提供互连过程。该过程包括以下步骤。首先，设置至少具有导电区域的半导体基板。接下来，形成具有接触孔的电介质层以覆盖半导体基底，其中接触孔暴露部分导电区域。然后，对覆盖有电介质层的半导体基板进行热处理。最后，在电介质层上形成导电层，其中导电层通过接触孔与导电区电连接。

129. 发明授权

US07544616B2 Methods of forming nitride read only memory and word lines thereof 有权
标题翻译：形成氮化物的方法只读存储器及其字线
公开(公告)号：US07544616B2
公开(公告)日：2009-06-09
申请号：US11874061
申请日：2007-10-17
申请人： Chi-Pin Lu , Ling-Wu Yang
发明人： Chi-Pin Lu , Ling-Wu Yang
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L27/11568 , H01L21/0337 , H01L21/32139 , H01L29/513 , H01L29/792
摘要： A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.
摘要翻译：形成存储器字线的方法包括提供衬底并在衬底上形成导电层。在导电层上形成金属硅化物层，在金属硅化物层上形成掩模图形。覆盖掩模图案的掩模衬垫和金属硅化物层的表面形成在衬底上以缩短字线区域之间的距离。对掩模衬垫和掩模图案进行蚀刻处理，直到暴露金属硅化物层的部分表面。通过利用掩模衬垫和掩模图案作为掩模，蚀刻金属硅化物层和导电层以形成字线。金属硅化物层的硅含量必须小于或等于2，以减少字线之间的桥接故障率。

130. 发明申请

US20070174211A1 AUTOMATIC PACKAGING SYSTEM AND METHOD 审中-公开
标题翻译：自动包装系统及方法
公开(公告)号：US20070174211A1
公开(公告)日：2007-07-26
申请号：US11308950
申请日：2006-05-29
申请人： CHUN-NAN OU , Lin Yan , Zhi-Wei Wang , Min Guo , Yu-Wu Yang , Lin-Sheng Hu
发明人： CHUN-NAN OU , Lin Yan , Zhi-Wei Wang , Min Guo , Yu-Wu Yang , Lin-Sheng Hu
IPC分类号： G06F17/00 , G06G7/00
CPC分类号： G06Q50/04 , G06Q30/0283 , Y02P90/30
摘要： An automatic packaging system is provided. The automatic packaging system includes a user interface, a selection-controlling module, an alarm-controlling module, and a package module. The user interface is for receiving user input. The selection-controlling module is for enabling and controlling a vibrating plate to select parts according to the user input, and generating a detection signal. The alarm-controlling module is for generating a package signal according to the detection signal and the user input. The package module is for packaging the parts according to the package signal.
摘要翻译：提供自动包装系统。自动包装系统包括用户界面，选择控制模块，报警控制模块和包装模块。用户界面用于接收用户输入。所述选择控制模块用于启用和控制振动板以根据用户输入选择部件，并产生检测信号。报警控制模块用于根据检测信号和用户输入产生封装信号。封装模块用于根据封装信号封装零件。

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