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111. 发明授权

US07220612B2 Liquid crystal display device and fabricating method thereof 有权
标题翻译：液晶显示装置及其制造方法
公开(公告)号：US07220612B2
公开(公告)日：2007-05-22
申请号：US11168313
申请日：2005-06-29
申请人： Byung Chul Ahn , Joo Soo Lim , Byung Ho Park
发明人： Byung Chul Ahn , Joo Soo Lim , Byung Ho Park
IPC分类号： H01L21/336
CPC分类号： H01L27/12 , H01L27/124 , H01L27/1288 , H01L29/41733 , H01L29/458 , H01L29/4908 , Y10S438/951
摘要： A thin film transistor substrate and a fabricating method thereof for simplifying a process are disclosed. In a liquid crystal display device according to the present invention, a gate line is provided on a substrate. A data line crosses the gate line with having a gate insulating film therebetween to define a pixel area. A thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, a drain electrode opposed to the source electrode and a semiconductor layer for defining a channel between the source electrode and the drain electrode. A pixel electrode is connected to the drain electrode and is provided at said pixel area. Herein, said data line, said source electrode and said drain electrode have a double-layer structure in which a source/drain metal pattern and a transparent conductive pattern are built. Said pixel electrode is formed by an extension of the transparent conductive pattern of the drain electrode. A protective film makes a border with the transparent conductive pattern and provided at the remaining area thereof.
摘要翻译：公开了一种用于简化工艺的薄膜晶体管基板及其制造方法。在根据本发明的液晶显示装置中，在基板上设置栅极线。数据线与栅极线交叉，其间具有栅极绝缘膜以限定像素区域。薄膜晶体管包括连接到栅极线的栅电极，连接到数据线的源电极，与源电极相对的漏电极和用于限定源电极和漏极之间的沟道的半导体层。像素电极连接到漏电极并设置在所述像素区域。这里，所述数据线，所述源电极和所述漏极具有其中构成源极/漏极金属图案和透明导电图案的双层结构。所述像素电极由漏电极的透明导电图案的延伸形成。保护膜与透明导电图案形成边界并设置在其余的区域。

112. 发明授权

US07078279B2 Manufacturing method of a thin film transistor array substrate 有权
标题翻译：薄膜晶体管阵列基板的制造方法
公开(公告)号：US07078279B2
公开(公告)日：2006-07-18
申请号：US10950493
申请日：2004-09-28
申请人： Soon Sung Yoo , Heung Lyul Cho
发明人： Soon Sung Yoo , Heung Lyul Cho
IPC分类号： H01L21/336 , H01L29/41 , G02F1/1343
CPC分类号： G02F1/13458 , G02F1/1368 , G02F2001/136231 , G02F2201/50 , H01L27/12 , H01L27/124 , H01L27/1288 , Y10S438/951
摘要： A method of manufacturing a thin film transistor capable of simplifying a substrate structure and a manufacturing process is disclosed. The method of manufacturing a thin film transistor array substrate includes involves a three-round mask process, which includes: forming a gate pattern on a substrate; forming a gate insulating film on the substrate having the gate pattern thereon; forming a source/drain pattern and a semiconductor pattern; forming a passivation film to protect the thin film transistor on an entire surface of the substrate; forming a photo-resist pattern on the passivation film; patterning the passivation film using the photo-resist pattern to form a passivation film pattern; and forming a transparent electrode pattern being extended from a lateral surface of the passivation film pattern and formed at an area except for the passivation film pattern.
摘要翻译：公开了一种能够简化衬底结构和制造工艺的制造薄膜晶体管的方法。制造薄膜晶体管阵列基板的方法包括三向掩模工艺，其包括：在基板上形成栅极图案; 在其上具有栅极图案的衬底上形成栅极绝缘膜; 形成源极/漏极图案和半导体图案; 形成钝化膜，以在衬底的整个表面上保护薄膜晶体管; 在钝化膜上形成光刻胶图案; 使用光致抗蚀剂图案来图案化钝化膜以形成钝化膜图案; 以及形成从钝化膜图案的侧表面延伸并形成在除了钝化膜图案之外的区域的透明电极图案。

113. 发明申请

US20050170628A1 Forming a contact in a thin-film device 失效
标题翻译：在薄膜装置中形成接触
公开(公告)号：US20050170628A1
公开(公告)日：2005-08-04
申请号：US10770083
申请日：2004-01-31
申请人： Manish Sharma , Thomas Anthony , Heon Lee
发明人： Manish Sharma , Thomas Anthony , Heon Lee
IPC分类号： H01L21/027 , H01L21/033 , H01L21/311 , H01L21/44 , H01L43/12
CPC分类号： H01L21/0331 , H01L21/0272 , H01L21/31144 , H01L43/12 , Y10S438/951
摘要： An aspect of the present invention is a method of forming a contact in a thin-film device. The method includes forming a liftoff stencil, depositing at least one material through the liftoff stencil, removing a portion of the liftoff stencil, forming a re-entrant profile with the remaining portion of the liftoff stencil and depositing a conductor material in contact with the at least one material on the re-entrant profile.
摘要翻译：本发明的一个方面是在薄膜器件中形成接触的方法。该方法包括形成剥离模板，将至少一种材料沉积通过剥离模板，去除剥离模板的一部分，与剥离模板的剩余部分形成重新进入的模型并且沉积导体材料与所述脱模模板接触。至少一个材料在入口轮廓。

114. 发明授权

US06881688B2 Method of fabricating a vertically profiled electrode and semiconductor device comprising such an electrode 失效
标题翻译：制造垂直异型电极的方法和包括这种电极的半导体器件
公开(公告)号：US06881688B2
公开(公告)日：2005-04-19
申请号：US10323817
申请日：2002-12-20
申请人： Bernd E. Maile
发明人： Bernd E. Maile
IPC分类号： H01L21/027 , H01L21/28 , H01L21/285 , H01L29/423 , H01L21/00
CPC分类号： H01L21/28114 , H01L21/0272 , H01L21/28587 , H01L29/42376 , Y10S438/945 , Y10S438/948 , Y10S438/951
摘要： A method of fabricating a vertically profiled electrode like a T-gate 40 on a semiconductor substrate 20 is described. The method comprises providing a resist structure 34 on the substrate 20, the resist structure 34 containing at least a first resist pattern 24′ arranged on the substrate 20 and having a first opening 26, the first resist being negative resist, and a second resist pattern 32 having a second opening 30 surrounding the first opening 26. The vertical profile of the gate electrode 40 is defined by the contours and the relative location of the first and the second opening 26, 30. On the resist structure 34 a metal 38 is deposited and lift-off is performed to remove the second resist 32 together with the metal 38 deposited thereon.
摘要翻译：描述了在半导体衬底20上制造如T形门40的垂直异形电极的方法。该方法包括在基板20上设置抗蚀剂结构34，抗蚀剂结构34至少包含布置在基板20上的第一抗蚀剂图案24'，并具有第一开口26，第一抗蚀剂为负型抗蚀剂，第二抗蚀剂图案 32具有围绕第一开口26的第二开口30。栅电极40的垂直轮廓由第一和第二开口26,30的轮廓和相对位置限定。在抗蚀剂结构34上沉积金属38并进行剥离以与沉积在其上的金属38一起去除第二抗蚀剂32。

115. 发明授权

US06800921B1 Method of fabricating a polysilicon capacitor utilizing fet and bipolar base polysilicon layers 有权
标题翻译：使用电子和双极基底多晶硅层制造多晶硅电容器的方法
公开(公告)号：US06800921B1
公开(公告)日：2004-10-05
申请号：US09516615
申请日：2000-03-01
申请人： Douglas Duane Coolbaugh , Gregory Gower Freeman , Seshadri Subbanna
发明人： Douglas Duane Coolbaugh , Gregory Gower Freeman , Seshadri Subbanna
IPC分类号： H01L27108
CPC分类号： H01L28/40 , H01L21/8249 , H01L27/0635 , Y10S438/951
摘要： A method of forming a poly-poly capacitor, a MOS transistor, and a bipolar transistor simultaneously on a substrate comprising the steps of depositing and patterning a first layer of polysilicon on the substrate to form a first plate electrode of said capacitor and on an electrode of the MOS transistor, and depositing and patterning a second layer of polysilicon on the substrate to form a second plate electrode of said capacitor and an electrode of the bipolar transistor.
摘要翻译：一种在衬底上同时形成多晶硅多晶硅电容器，MOS晶体管和双极晶体管的方法，包括以下步骤：在衬底上沉积和构图第一层多晶硅以形成所述电容器的第一平板电极和电极并且在衬底上沉积和构图第二层多晶硅以形成所述电容器的第二平板电极和双极晶体管的电极。

116. 发明申请

US20040185675A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY (MRAM) CELL PATTERNING 失效
标题翻译：磁阻随机访问存储器（MRAM）单元格格式
公开(公告)号：US20040185675A1
公开(公告)日：2004-09-23
申请号：US10677803
申请日：2003-10-02
申请人： Micron Technology, Inc.
发明人： Yong Lu , Theodore Zhu
IPC分类号： H01L021/31
CPC分类号： H01L27/222 , H01L43/12 , Y10S438/951
摘要： A process that advantageously forms MRAM cells without the application of ion beam milling processes. Unlike conventional processes that rely on ion beam milling processes to remove materials from a magnetoresistive sandwich from areas other than areas that will later form MRAM cell bodies, this process forms a layer of photoresist over areas other than those areas that correspond to MRAM cell bodies. The photoresist is lifted off after the deposition of a magnetoresistive sandwich that forms the MRAM cell bodies, thereby safely removing the magnetoresistive sandwich from undesired areas while maintaining the magnetoresistive sandwich in the areas corresponding to MRAM cell bodies.
摘要翻译：有利地形成MRAM电池而不施加离子束研磨工艺的方法。不同于依靠离子束研磨工艺从除了稍后形成MRAM单元体的区域之外的区域从磁阻三明治去除材料的常规工艺，该工艺在除了对应于MRAM单元体的那些区域之外的区域上形成光致抗蚀剂层。在形成MRAM单元体的磁阻三明治的沉积之后，光致抗蚀剂被剥离，从而从不期望的区域安全地去除磁阻三明治，同时在对应于MRAM单元体的区域中保持磁阻三明治。

117. 发明授权

US06737202B2 Method of fabricating a tiered structure using a multi-layered resist stack and use 有权
标题翻译：使用多层抗蚀剂叠层制造分层结构的方法和用途
公开(公告)号：US06737202B2
公开(公告)日：2004-05-18
申请号：US10081199
申请日：2002-02-22
申请人： Kathleen Ann Gehoski , Laura Popovich , David P. Mancini , Doug J. Resnick
发明人： Kathleen Ann Gehoski , Laura Popovich , David P. Mancini , Doug J. Resnick
IPC分类号： H01L21302
CPC分类号： H01L21/0272 , H01L21/0274 , H01L29/42316 , Y10S438/951
摘要： An improved and novel method of forming a tiered structure, such as a T-gate structure, including the fabrication of a stabilized resist layer that provides for the prevention of interlayer intermixing with the deposition of subsequent resist layers. The method includes patterning a base resist layer to provide for an opening which will form the stem of the tiered structure and subsequently stabilizing the resist base layer without deforming the stem opening. Next, a resist stack is deposited on an uppermost surface of the stabilized resist layer. Patterning the resist stack provides for an opening on an uppermost layer or portion, and a reentrant profile in a portion of the resist stack adjacent the stabilized resist layer. Metallization and subsequent removal of the resist layers results in a tiered structure, such as a T-gate structure, formed using only low to medium molecular weight, linear polymeric materials such as those used in positive optical resists in optical lithography.
摘要翻译：形成诸如T型栅结构的分层结构的改进和新颖的方法，包括制造稳定的抗蚀剂层，其提供防止与随后的抗蚀剂层的沉积的层间混合。该方法包括图案化基底抗蚀剂层以提供将形成分层结构的杆的开口，并且随后使抗蚀剂基底层稳定，而不会使阀杆开口变形。接着，在稳定化的抗蚀剂层的最上表面上淀积抗蚀剂叠层。抗蚀剂层的图案化提供了最上层或部分上的开口，以及在抗蚀剂层的与稳定的抗蚀剂层相邻的部分中的折入轮廓。金属化和随后的抗蚀剂层的去除导致仅使用低分子量至中等分子量的线性聚合物材料（例如在光学光刻中的正光学抗蚀剂中使用的那些）形成的分层结构，例如T形栅结构。

118. 发明授权

US06677165B1 Magnetoresistive random access memory (MRAM) cell patterning 有权
标题翻译：磁阻随机存取存储器（MRAM）细胞图案化
公开(公告)号：US06677165B1
公开(公告)日：2004-01-13
申请号：US10393713
申请日：2003-03-20
申请人： Yong Lu , Theodore Zhu
发明人： Yong Lu , Theodore Zhu
IPC分类号： H01L218242
CPC分类号： H01L27/222 , H01L43/12 , Y10S438/951
摘要： A process that advantageously forms MRAM cells without the application of ion beam milling processes. Unlike conventional processes that rely on ion beam milling processes to remove materials from a magnetoresistive sandwich from areas other than areas that will later form MRAM cell bodies, this process forms a layer of photoresist over areas other than those areas that correspond to MRAM cell bodies. The photoresist is lifted off after the deposition of a magnetoresistive sandwich that forms the MRAM cell bodies, thereby safely removing the magnetoresistive sandwich from undesired areas while maintaining the magnetoresistive sandwich in the areas corresponding to MRAM cell bodies.
摘要翻译：有利地形成MRAM电池而不施加离子束研磨工艺的方法。不同于依靠离子束研磨工艺从除了稍后形成MRAM单元体的区域之外的区域从磁阻三明治去除材料的常规工艺，该工艺在除了对应于MRAM单元体的那些区域之外的区域上形成光致抗蚀剂层。在形成MRAM单元体的磁阻三明治的沉积之后，光致抗蚀剂被剥离，从而从不期望的区域安全地去除磁阻三明治，同时在对应于MRAM单元体的区域中保持磁阻三明治。

119. 发明授权

US06605519B2 Method for thin film lift-off processes using lateral extended etching masks and device 有权
标题翻译：使用横向延伸蚀刻掩模和器件的薄膜剥离工艺的方法
公开(公告)号：US06605519B2
公开(公告)日：2003-08-12
申请号：US09846214
申请日：2001-05-02
申请人： David G. Lishan
发明人： David G. Lishan
IPC分类号： H01L2122
CPC分类号： H01L29/66848 , H01L21/28 , H01L21/28587 , H01L29/66242 , H01L29/66318 , H01L29/66863 , Y10S438/951
摘要： A method for forming an etching mask structure on a substrate includes etching the substrate, laterally expanding the etching mask structure, and depositing a self-aligned metal layer that is aligned to the originally masked area. The etching can be isotropic or anisotropic. The self-aligned metal layer can be distanced from the original etching masked area based on the extent of the intentionally laterally expanded etching mask layer. Following metal deposition, the initial mask structure can be removed, thus lifting off the metal atop it. The etching mask structure can be a resist and can be formed using conventional photolithography materials and techniques and can have nearly vertical sidewalls. The lateral extension can include a silylation technique of the etching mask layer following etching. The above method can be utilized to form bipolar, hetero-bipolar, or field effect transistors.
摘要翻译：在衬底上形成蚀刻掩模结构的方法包括蚀刻衬底，横向扩展蚀刻掩模结构，以及沉积与原来掩蔽区域对准的自对准金属层。蚀刻可以是各向同性或各向异性的。基于有意横向扩展的蚀刻掩模层的程度，自对准金属层可以远离原始蚀刻掩模区域。在金属沉积之后，可以去除初始掩模结构，从而将金属顶起来。蚀刻掩模结构可以是抗蚀剂，并且可以使用常规的光刻材料和技术形成，并且可以具有几乎垂直的侧壁。侧向延伸可以包括蚀刻后的蚀刻掩模层的甲硅烷基化技术。上述方法可用于形成双极型，异质双极型或场效应晶体管。

120. 发明授权

US6107172A Controlled linewidth reduction during gate pattern formation using an SiON BARC 失效
标题翻译：使用SiON BARC在栅极图案形成期间的受控线宽减小
公开(公告)号：US6107172A
公开(公告)日：2000-08-22
申请号：US905104
申请日：1997-08-01
申请人： Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
发明人： Chih-Yuh Yang , Scott A. Bell , Daniel Steckert
IPC分类号： H01L21/3213 , H01L21/3205 , H01L21/302 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/32139 , Y10S438/951 , Y10S438/952
摘要： A gate is formed by creating a wafer stack, that includes a gate conductive layer over a substrate layer, depositing a SiO.sub.x N.sub.y layer over the conductive layer to act as a bottom anti-reflective coating (BARC), and forming a resist mask on the SiO.sub.x N.sub.y layer. Next, the resist mask is isotropically etched to further reduce the critical dimensions of the gate pattern formed therein, and then the underlying BARC and wafer stack are etched to form a gate out of the conductive layer.
摘要翻译：通过产生晶片堆叠形成栅极，该晶片堆叠包括在衬底层上的栅极导电层，在导电层上方沉积SiOxNy层以充当底部抗反射涂层（BARC），并在SiO x N y上形成抗蚀剂掩模层。接下来，抗蚀剂掩模被各向同性地蚀刻以进一步减小在其中形成的栅极图案的临界尺寸，然后蚀刻下面的BARC和晶片叠层以在导电层外形成栅极。

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