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111. 发明专利

JP2013069139A Arithmetic processing unit and method for controlling arithmetic processing unit 审中-公开
标题翻译：算术处理单元和控制算术处理单元的方法
公开(公告)号：JP2013069139A
公开(公告)日：2013-04-18
申请号：JP2011207541
申请日：2011-09-22
申请人： Fujitsu Ltd , 富士通株式会社
发明人： MARUYAMA MASAHARU
IPC分类号： G06F12/12 , G06F12/10
CPC分类号： G06F12/1036 , G06F2212/684
摘要： PROBLEM TO BE SOLVED: To provide an arithmetic processing unit for preventing a logical address space whose use frequency is high from being frequently replaced.SOLUTION: An arithmetic processing unit connected to a storage device having a buffer area in which an address conversion counterpart is stored includes: an LRU register for storing the number of a logical address register whose use history is the oldest among a plurality of logical address registers; a reading section (S502) for, when the logical address included in an access request to the storage device is not present in the range of a logical address space from a lower limit logical address stored in a lower limit logical address register to an upper limit logical address stored in an upper limit logical address register, reading the number of the logical address register stored by the LRU register; and a setting section (S410) for invalidating the logical address register of the read number, and for setting the logical address space corresponding to the logical address included in the access request in the invalidated logical address register.
摘要翻译：要解决的问题：提供一种用于防止经常更换使用频率高的逻辑地址空间的运算处理单元。解决方案：连接到具有其中存储地址转换对应物的缓冲区的存储装置的算术处理单元包括：LRU寄存器，用于存储多个存储器中的使用历史最早的逻辑地址寄存器的编号逻辑地址寄存器; 读取部（S502），当存储装置的访问请求中包含的逻辑地址不存在于从下限逻辑地址寄存器中存储的下限逻辑地址到上限的逻辑地址空间的范围内时存储在上限逻辑地址寄存器中的逻辑地址，读取LRU寄存器存储的逻辑地址寄存器的编号; 以及用于使读取的号码的逻辑地址寄存器无效并用于将与访问请求中包括的逻辑地址相对应的逻辑地址空间设置在无效逻辑地址寄存器中的设置部分（S410）。版权所有（C）2013，JPO＆INPIT

112. 发明专利

JP2011181095A Maintaining processor resource during architectural event 有权
标题翻译：在建筑活动期间维护加工者资源
公开(公告)号：JP2011181095A
公开(公告)日：2011-09-15
申请号：JP2011106137
申请日：2011-05-11
申请人： Intel Corp , インテルコーポレイション
发明人： BRANDT JASON , MONDAL SANJOY K , UHLIG RICHARD , NEIGER GILBERT , GEORGE ROBERT
IPC分类号： G06F9/48 , G06F12/10
CPC分类号： G06F12/1027 , G06F9/45533 , G06F9/45558 , G06F9/4843 , G06F12/0292 , G06F12/0804 , G06F12/0891 , G06F12/1036 , G06F12/1063 , G06F12/109 , G06F12/12 , G06F12/123 , G06F2009/45583 , G06F2009/45591 , G06F2212/1016 , G06F2212/152 , G06F2212/30 , G06F2212/50 , G06F2212/604 , G06F2212/657 , G06F2212/68 , G06F2212/683 , G06F2212/684 , G06F2212/69
摘要： PROBLEM TO BE SOLVED: To reduce overhead associated with switching the context of an address space. SOLUTION: A processor includes: a control register which stores an address based on a page directory corresponding to the address space; a conversion look-aside buffer which includes an entry containing a field of an address space identifier; and an execution logic which executes an "MOV to control register" command in order to switch between the address spaces without flashing the conversion look-aside buffer. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：减少与切换地址空间的上下文相关的开销。解决方案：处理器包括：控制寄存器，其基于与地址空间相对应的页目录来存储地址; 转换后备缓冲器，其包括包含地址空间标识符的字段的条目; 以及执行“MOV到控制寄存器”命令以便在地址空间之间切换而不闪烁转换后备缓冲器的执行逻辑。版权所有（C）2011，JPO＆INPIT

113. 发明授权

KR101893451B1 메모리 관리 방법 및 장치 有权
公开(公告)号：KR101893451B1
公开(公告)日：2018-10-04
申请号：KR1020167029979
申请日：2015-04-15
申请人： 후아웨이 테크놀러지 컴퍼니 리미티드
发明人： 류야오 , 황융빙 , 천밍위 , 추이쩌한 , 천리청 , 롼위안
IPC分类号： G06F12/1027
CPC分类号： G06F12/1027 , G06F3/0608 , G06F3/0619 , G06F3/0647 , G06F3/0652 , G06F3/0664 , G06F3/0685 , G06F12/1009 , G06F2212/1024 , G06F2212/684
摘要： 본발명의실시예는메모리관리방법및 장치를제공하고, 이러한방법은, 메모리관리기가, 메모리액세스요청을수신하는단계 - 메모리액세스요청은가상어드레스를가짐 -; 메모리관리기가 TLB 및메모리에서가상어드레스에대응하는페이지테이블엔트리를찾지못하면, 가상어드레스의페이지오류유형을결정하는단계; 가상어드레스의페이지오류유형이빈 페이지로인한페이지오류이면, 메모리관리기가대응하는페이지를가상어드레스에할당하는단계 - 빈페이지로인한페이지오류는대응하는페이지가가상어드레스에할당되지않은것을의미함 -; 메모리관리기가, 가상어드레스에대응하는페이지테이블엔트리를메모리및 TLB에업데이트하는단계를포함한다. 가상어드레스의페이지오류유형을결정하는단계에의해, 빈페이지로인한페이지오류가발생하면, 메모리관리기는페이지오류를생성하지않고, 대응하는페이지를가상어드레스에할당한다. 따라서, 실시예의방법은페이지오류의발생횟수를줄이고, 메모리관리효율이개선된다.

114. 发明公开

KR20180013924A 메모리 관리 유닛들을 위한 멀디-스레드 변환 및 트랜잭션 재-순서화 审中-公开
标题翻译：内存管理单元的多线程转换和事务重新排序
公开(公告)号：KR20180013924A
公开(公告)日：2018-02-07
申请号：KR20177034178
申请日：2016-04-27
IPC分类号： G06F12/0891 , G06F12/0844 , G06F12/1036 , G06F12/1045
CPC分类号： G06F12/1063 , G06F12/0806 , G06F12/0842 , G06F12/0844 , G06F12/0891 , G06F12/1009 , G06F12/1036 , G06F2212/1024 , G06F2212/50 , G06F2212/655 , G06F2212/682 , G06F2212/683 , G06F2212/684
摘要： 시스템들및 방법들은멀티스레드메모리관리유닛(MMU)에서어드레스변환들을수행하는것과관련된다. 2개또는그 초과의어드레스변환요청들은멀티스레드 MMU에의해수신되고시스템메모리의어드레스들로의어드레스변환들을리트리브하도록병렬로프로세싱될수 있다. 어드레스변환들이멀티스레드 MMU의변환캐시에존재하는경우, 어드레스변환들이변환캐시로부터수신되고변환된어드레스들을사용하여시스템메모리의액세스를위해스케줄링될수 있다. 변환캐시에서미스가존재하는경우, 2개또는그 초과의어드레스변환요청들은 2개또는그 초과의변환테이블워크들에서병렬로스케줄링될수 있다.
摘要翻译：系统和方法涉及在多线程存储器管理单元（MMU）中执行地址转换。多线程MMU可以接收两个或更多地址转换请求并且并行处理以检索到系统存储器中的地址的地址转换。如果地址转换位于多线程MMU的转换缓存中，则可以从转换缓存接收地址转换并且使用转换后的地址调度以访问系统存储器。如果翻译缓存中存在遗漏，则可以在两个或更多翻译餐具中并行调度两个或更多个地址翻译请求。

115. 发明授权

KR101072645B1 마이크로프로세서내의 예외트리거링 페이지를 표시하기 위한 방법 및 장치 有权
标题翻译：在微处理器中显示异常页的方法和系统
公开(公告)号：KR101072645B1
公开(公告)日：2011-10-11
申请号：KR1020097002355
申请日：2007-07-13
申请人： 퀄컴 인코포레이티드
发明人： 코드레슈,루시안 , 플론드케,에리히 , 아메드,무하메드 , 잔자남,비자야쿠마르
IPC分类号： G06F12/10 , G06F9/06 , G06F7/00
CPC分类号： G06F12/1009 , G06F12/1027 , G06F2212/684
摘要： 본발명은소프트웨어-관리페이지테이블내의어느페이지가예컨대디지털신호프로세서와같은마이크로프로세서내에서예외를트리거링하는지를표시하기위한방법및 시스템에관한것이며, 소프트웨어-관리변환참조버퍼(TLB: translation look-aside buffer) 모듈은예컨대페치명령(fetch instruction)과같은긴 명령어워드 (VLIW: Very Long Instruction Word) 패킷내의명령에의하여생성된가상어드레스를수신하며, 이가상어드레스와각각의저장된 TLB 엔트리를비교한다. 만일매치(match)가존재하면, TLB 모듈은명령에대한대응하는매핑된물리어드레스를출력한다. 그렇치않고, 만일 VLIW 패킷이 2개의페이지들에걸쳐있으면(여기서, 제 1 페이지는 TLB 모듈내의 TLB 엔트리로서제공되며제 2 페이지는저장된 TLB 엔트리들로부터미싱(missing)된다), 제어레지스터의데이터필드내의표시비트(indication bit)는소프트웨어관리유닛에대한 TLB 미스예외를식별하기위하여세팅된다. 소프트웨어관리유닛은레지스터로부터표시비트정보를검색하고, 미싱(missing) 페이지정보를검색하기위하여표시비트정보를사용하여소프트웨어-관리페이지테이블내의페이지테이블룩-업(look-up)을수행한다. 다음으로, 미싱페이지정보는명령들의패킷의다음가상어드레스변환및 실행을위하여 TLB 모듈내의새로운 TLB 엔트리에기록된다.

116. 发明授权

KR1019930001885B1 가상 메모리의 페이지 테이블 失效
标题翻译：虚拟内存中的页表
公开(公告)号：KR1019930001885B1
公开(公告)日：1993-03-19
申请号：KR1019890007792
申请日：1989-06-05
申请人： 디지탈 이큅먼트 코포레이션
发明人： 로버트이.스튜어트 , 티모시이레너드 , 세리츠이-츄안리
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F2212/684
摘要： 내용 없음.

117. 发明申请

WO2018080684A1 NESTED EXCEPTION HANDLING 审中-公开
标题翻译：嵌套异常处理
公开(公告)号：WO2018080684A1
公开(公告)日：2018-05-03
申请号：PCT/US2017/053088
申请日：2017-09-22
申请人： INTEL CORPORATION
发明人： XING, Bin
IPC分类号： G06F21/53 , G06F21/54 , G06F21/56
CPC分类号： G06F12/1009 , G06F9/30054 , G06F9/30076 , G06F9/3802 , G06F9/3861 , G06F12/08 , G06F12/109 , G06F12/12 , G06F12/128 , G06F12/145 , G06F21/79 , G06F2212/1052 , G06F2212/657 , G06F2212/684 , G06F2212/70
摘要： An example system that includes a processor and a memory device. The processor may include multiple execution units to execute instructions and a memory device coupled to the processor. The memory device stores the instructions in an unprotected region and a protected region. The processor may determine that a first exception occurred while executing a first set of instructions for an application stored in a secured page of the protected region. The processor may invoke a first subroutine to forward exception context for the first exception to a second subroutine, where the first subroutine is stored in the protected region and the second subroutine is stored in the unprotected region. The processor may invoke, by the second subroutine, a third subroutine to execute a second set of instructions associated with the exception context for the first exception.
摘要翻译：
包含处理器和存储器设备的示例系统。处理器可以包括执行指令的多个执行单元和耦合到处理器的存储器设备。存储设备将指令存储在未受保护的区域和受保护的区域中。处理器可以确定在执行存储在受保护区域的受保护页面中的应用的第一组指令时发生第一异常。处理器可以调用第一子例程来将用于第一例外的异常上下文转发到第二子例程，其中第一子例程存储在受保护区域中并且第二子例程存储在未受保护区域中。处理器可以通过第二子例程调用第三子例程来执行与第一例外的异常上下文相关联的第二组指令。

118. 发明申请

WO2017129932A1 MEMORY ADDRESS TRANSLATION MANAGEMENT 审中-公开
标题翻译：存储器地址转换管理
公开(公告)号：WO2017129932A1
公开(公告)日：2017-08-03
申请号：PCT/GB2016/054009
申请日：2016-12-21
申请人： ARM LIMITED
发明人： PARKER, Jason
IPC分类号： G06F12/1009 , G06F12/14 , G06F9/50
CPC分类号： G06F12/1009 , G06F9/50 , G06F12/1441 , G06F2212/1052 , G06F2212/151 , G06F2212/651 , G06F2212/684
摘要： A data processing apparatus (2) includes memory management circuitry (18) for managing a two-stage address translation from a virtual address VA to an intermediate physical address IPA and then from the intermediate physical address IPA to a physical address PA. The first stage of the translation is performed using first stage translation data (22) controlled by a virtual machine program executing within a virtual machine execution environment provided by a hypervisor program which manages second stage translation data (24) for performing a second stage translation. If a region of memory is designated as a virtual machine private region accessible to a given virtual machine, but inaccessible to the hypervisor program, and also as a device region, then the memory management circuitry (18) performs private-device region management in respect of that region (i.e. the intermediate physical address may not be altered by the second stage translation). If a region is not both a virtual machine private region and a device region, then the memory management circuitry (18) performs non-private device management thereon.
摘要翻译：数据处理装置（2）包括存储器管理电路（18），用于管理从虚拟地址VA到中间物理地址IPA，然后从中间物理地址IPA到一个物理地址PA。使用由管理用于执行第二阶段翻译的第二阶段翻译数据（24）的管理程序程序提供的虚拟机执行环境内执行的虚拟机程序控制的第一阶段翻译数据（22）执行翻译的第一阶段。如果存储器区域被指定为给定虚拟机可访问但管理程序程序不可访问的虚拟机专用区域，并且还被指定为设备区域，则存储器管理电路（18）在方面执行私有设备区域管理（即中间物理地址可能不会被第二阶段转换所改变）。如果一个区域不是虚拟机专用区域和设备区域，则存储器管理电路（18）对其进行非专用设备管理。

119. 发明申请

WO2016204913A1 PROTECTED MEMORY REGIONS 审中-公开
标题翻译：保护的记忆区
公开(公告)号：WO2016204913A1
公开(公告)日：2016-12-22
申请号：PCT/US2016/032948
申请日：2016-05-18
申请人： MICROSOFT TECHNOLOGY LICENSING, LLC
发明人： SELL, John V.
IPC分类号： G06F21/52 , G06F12/14
CPC分类号： G06F21/604 , G06F9/45558 , G06F12/1027 , G06F12/14 , G06F12/145 , G06F12/1491 , G06F21/52 , G06F21/566 , G06F2009/45583 , G06F2009/45587 , G06F2212/1052 , G06F2212/151 , G06F2212/657 , G06F2212/684 , G06F2221/034
摘要： A data processing machine is configured to include one or more buried memory zones that are not intelligibly accessible to user software and to operating system software or hypervisor software within the data processing machine. At least one of hardware and firmware are configured to intelligibly access at least one of the buried memory zones so as to store therein, metadata defining one or more extents of a respective one or more protected regions (PR's) that are constituted in other memory areas of the data processing machine. The stored metadata defines constraints for the corresponding PR's including at least one of corresponding operational constraints and/or operational requirements that respectively constrain the operations performed by or on the data of the PR's.
摘要翻译：数据处理机被配置为包括用户软件不可理解地访问的一个或多个掩埋的存储器区域以及数据处理机器内的操作系统软件或管理程序软件。硬件和固件中的至少一个被配置为可智能地访问至少一个埋藏的存储器区域，以便在其中存储定义在其它存储区域中构成的相应的一个或多个受保护区域（PR）的一个或多个范围的元数据的数据处理机。所存储的元数据定义了对应PR的约束，包括分别限制由PR执行的操作或由PR的数据执行的操作的对应操作约束和/或操作要求中的至少一个。

120. 发明申请

WO2015057857A1 COMPUTER PROCESSOR EMPLOYING DEDICATED HARDWARE MECHANISM CONTROLLING THE INITIALIZATION AND INVALIDATION OF CACHE LINES 审中-公开
标题翻译：计算机处理器采用专用硬件机制控制缓存线路的初始化和无效化
公开(公告)号：WO2015057857A1
公开(公告)日：2015-04-23
申请号：PCT/US2014/060721
申请日：2014-10-15
申请人： MILL COMPUTING, INC.
发明人： GODARD, Roger, Rawson , KAHLICH, Arthur, David , HARDY, Norman , BAUM, Allen, J.
IPC分类号： G06F12/08
CPC分类号： G06F9/30032 , G06F9/30145 , G06F9/3826 , G06F9/3828 , G06F12/0292 , G06F12/0811 , G06F12/0864 , G06F12/0893 , G06F12/0897 , G06F12/1009 , G06F12/1027 , G06F12/1045 , G06F17/30286 , G06F2212/1024 , G06F2212/1028 , G06F2212/283 , G06F2212/6032 , G06F2212/608 , G06F2212/684 , Y02D10/13
摘要： A computer processing system includes execution logic that generates memory requests that are supplied to a hierarchical memory system. The computer processing system includes a hardware map storing a number of entries associated with corresponding cache lines, where each given entry of the hardware map indicates whether a corresponding cache line i) currently stores valid data in the hierarchical memory system, or ii) does not currently store valid data in hierarchical memory system and should be interpreted as being implicitly zero throughout.
摘要翻译：计算机处理系统包括产生提供给分层存储器系统的存储器请求的执行逻辑。计算机处理系统包括存储与对应的高速缓存行相关联的多个条目的硬件映射，其中硬件映射的每个给定条目指示对应的高速缓存行i）当前是否在分层存储器系统中存储有效数据，或者ii）不目前在分层存储系统中存储有效数据，并且应该被解释为整体为零。

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