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    • 115. 发明授权
      US5088023A Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device 失效
    • Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device
    • US5088023A
    • 1992-02-11
    • US358523
    • 1989-05-30
    • Hideo Nakamura , Terumi Sawase
    • Hideo Nakamura , Terumi Sawase
    • G06F12/00 , G06F12/06 , G06F13/16 , G06F15/17 , G06F15/78
    • G06F15/7842 , G06F15/786
    • The present invention discloses an integrated circuit having a data bus, an address bus, a processor and a memory each connected to the data bus and the address bus, a first transmitter for transmitting data inputted to a data terminal to the data bus, a second transmitter for transmitting data on the data bus to the data terminal, a third transmitter for transmitting an address inputted to an address terminal to the address bus, and signal generate means for generating signals to set the respective outputs from the first and third transmitters to the high impedance in response to a memory read request supplied from the processor, for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory to the data bus, the first transmitter, and the third transmitter to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to output data and an address from the processor to the data bus and the address bus, respectively to the high impedance in response to a memory read request from an external device, and for generating signals to set the respective outputs from the data output of processor module and the address output of processor module in response to a memory write request from an external device, the integrated circuit further including a fourth transmitter for transmitting an address on the address bus to the address terminal, wherein the signal generate means generates signals to set the outputs from the first and third transmitters to the high impedance in response to an external memory read request supplied from the processor, sets the respective outputs from the data output of memory module, the first transmitter, and the third transmitter to the high impedance in response to an external memory write request supplied from the processor, and responds to the read or write request from the external device in preference to the read or write request from the processor.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 120. 发明授权
      US4716522A Microcomputer system with buffer in peripheral storage control 失效
    • Microcomputer system with buffer in peripheral storage control
    • 微机系统具有缓冲区外设存储控制
    • US4716522A
    • 1987-12-29
    • US473861
    • 1983-03-10
    • Tsuneo Funabashi , Kazuhiko Iwasaki , Hideo Nakamura
    • Tsuneo Funabashi , Kazuhiko Iwasaki , Hideo Nakamura
    • G06F3/06 , G06F13/00 , G06F13/28
    • G06F3/0601 , G06F13/28 , G06F2003/0691
    • A microcomputer system has a peripheral storage control equipped with both a circuit which is responsive to a transfer command received from an MPU to set in a counter a transfer start address, which is designated subsequent to that command. The counter to supply an address for a buffer to control transfer of data from the output of the buffer to a common bus connected between the MPU and a RAM. A circuit is provided for controlling the aforementioned counter to count up in response to a transfer acknowledge signal which is subsequently received from a direct memory access control. In order that the data in the buffer may not be transferred to the RAM but may be rewritten, the peripheral storage control is further equipped with both a circuit for setting a rewrite address also received from the MPU in the counter, which is operative to identify the address of the selected buffer, in association with a rewrite command received from the MPU, and a circuit is also provided for applying the rewrite signal to the buffer each time the rewrite data is received after the setting operation from the MPU.
    • 微型计算机系统具有外围存储控制，该外围存储控制装置具有响应于从MPU接收到的传送命令的电路，在计数器中设置在该命令之后指定的传送起始地址。 该计数器为缓冲器提供地址，以控制从缓冲器的输出到连接在MPU和RAM之间的公共总线的数据传输。 提供电路，用于响应于随后从直接存储器访问控制接收的传送确认信号来控制上述计数器进行计数。 为了缓冲器中的数据可能不被传送到RAM但是可以被重写，外围存储控制还配备有用于设置也从计数器中的MPU接收的重写地址的电路，其可操作地识别 还提供与从MPU接收的重写命令相关联的所选择的缓冲器的地址和电路，用于在每次在来自MPU的设置操作之后接收到重写数据时，将重写信号施加到缓冲器。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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