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111. 发明授权

US08822306B2 Method for manufacturing a composite wafer having a graphite core, and composite wafer having a graphite core 有权
标题翻译：具有石墨芯的复合晶片的制造方法以及具有石墨芯的复合晶片
公开(公告)号：US08822306B2
公开(公告)日：2014-09-02
申请号：US13206029
申请日：2011-08-09
申请人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
发明人： Rudolf Berger , Hermann Gruber , Wolfgang Lehnert , Guenther Ruhl , Raimund Foerg , Anton Mauder , Hans-Joachim Schulze , Karsten Kellermann , Michael Sommer , Christian Rottmair , Roland Rupp
IPC分类号： H01L21/30
CPC分类号： H01L21/76254 , C30B25/186 , H01L21/02115 , H01L21/02282 , H01L21/02598 , H01L21/2007 , H01L21/265 , H01L21/3212 , H01L21/324 , H01L21/76251 , H01L29/1608 , H01L29/20 , H01L29/2003
摘要： According to an embodiment, a composite wafer includes a carrier substrate having a graphite layer and a monocrystalline semiconductor layer attached to the carrier substrate.
摘要翻译：根据实施例，复合晶片包括具有石墨层和附着到载体衬底的单晶半导体层的载体衬底。

112. 发明申请

US20140042595A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE INCLUDING GRINDING FROM A BACK SURFACE AND SEMICONDUCTOR DEVICE 有权
标题翻译：制造包括从背面和半导体器件研磨的半导体器件的方法
公开(公告)号：US20140042595A1
公开(公告)日：2014-02-13
申请号：US13571769
申请日：2012-08-10
申请人： Hans-Joachim Schulze , Anton Mauder
发明人： Hans-Joachim Schulze , Anton Mauder
IPC分类号： H01L29/02 , H01L21/78
CPC分类号： H01L29/06 , B24B7/228 , B24B37/013 , B24B37/042 , H01L21/302 , H01L21/304 , H01L21/30625 , H01L21/3247 , H01L21/764 , H01L21/78 , H01L22/26 , H01L29/66333
摘要： A cavity is etched from a front surface into a semiconductor substrate. After providing an etch stop structure at the bottom of the cavity, the cavity is closed. From a back surface opposite to the front surface the semiconductor substrate is grinded at least up to an edge of the etch stop structure oriented to the back surface. Providing the etch stop structure at the bottom of an etched cavity allows for precisely adjusting a thickness of a semiconductor body of a semiconductor device.
摘要翻译：将腔从前表面刻蚀成半导体衬底。在腔的底部提供蚀刻停止结构之后，空腔被关闭。从与前表面相对的后表面，半导体衬底至少被研磨到定向到后表面的蚀刻停止结构的边缘。在蚀刻腔的底部提供蚀刻停止结构允许精确地调节半导体器件的半导体本体的厚度。

113. 发明申请

US20130341673A1 Reverse Conducting IGBT 审中-公开
标题翻译：反向导通IGBT
公开(公告)号：US20130341673A1
公开(公告)日：2013-12-26
申请号：US13529166
申请日：2012-06-21
申请人： Frank Pfirsch , Dorothea Werber , Anton Mauder , Carsten Schaeffer
发明人： Frank Pfirsch , Dorothea Werber , Anton Mauder , Carsten Schaeffer
IPC分类号： H01L29/739
CPC分类号： H03K17/127 , H01L29/0615 , H01L29/0619 , H01L29/0696 , H01L29/0834 , H01L29/404 , H01L29/407 , H01L29/7393 , H01L29/7395 , H01L29/7397 , H03K3/01 , H03K17/66
摘要： A semiconductor device includes a first emitter region of a first conductivity type, a second emitter region of a second conductivity type complementary to the first conductivity type, and a drift region of the second conductivity type arranged in a semiconductor body. The first and second emitter regions are arranged between the drift region and a first electrode and are each connected to the first electrode. A device cell of a cell region includes a body region of the first conductivity type adjoining the drift region, a source region of the second conductivity type adjoining the body region, and a gate electrode adjacent the body region and dielectrically insulated from the body region by a gate dielectric. A second electrode is electrically connected to the source region and the body region. A floating parasitic region of the first conductivity type is disposed outside the cell region.
摘要翻译：半导体器件包括第一导电类型的第一发射极区域，与第一导电类型互补的第二导电类型的第二发射极区域和布置在半导体本体中的第二导电类型的漂移区域。第一和第二发射极区域布置在漂移区域和第一电极之间并且各自连接到第一电极。单元区域的器件单元包括邻接漂移区的第一导电类型的主体区域，与身体区域邻接的第二导电类型的源极区域和与身体区域相邻并且与身体区域电介质绝缘的栅电极，栅极电介质。第二电极电连接到源区域和身体区域。第一导电类型的浮置寄生区域设置在单元区域的外部。

114. 发明授权

US08614478B2 Method for protecting a semiconductor device against degradation, a semiconductor device protected against hot charge carriers and a manufacturing method therefor 有权
标题翻译：防止半导体器件劣化的方法，保护热电荷载流子的半导体器件及其制造方法
公开(公告)号：US08614478B2
公开(公告)日：2013-12-24
申请号：US12843326
申请日：2010-07-26
申请人： Anton Mauder , Hans-Joachim Schulze
发明人： Anton Mauder , Hans-Joachim Schulze
IPC分类号： H01L29/66
CPC分类号： H01L29/407 , H01L21/283 , H01L29/063 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792
摘要： A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided.
摘要翻译：提供了一种用于保护半导体器件免于其电特性劣化的方法。该方法包括提供具有形成介电半导体界面的第一半导体区域和带电介质层的半导体器件。第一半导体区域的多数电荷载流子是第一电荷类型。带电电介质层包括第一充电类型的固定电荷。固定电荷的每个面积的电荷载流子密度被配置为使得带电电介质层被屏蔽，以阻止在第一半导体区域中产生的热多数电荷载流子。此外，提供了防止热电荷载流子的半导体器件和形成半导体器件的方法。

115. 发明申请

US20120225540A1 Method for fabricating a porous semiconductor body region 有权
标题翻译：多孔半导体体区域的制造方法
公开(公告)号：US20120225540A1
公开(公告)日：2012-09-06
申请号：US13407728
申请日：2012-02-28
申请人： Hans-Joachim Schulze , Anton Mauder , Francisco Javier Santos Rodriguez
发明人： Hans-Joachim Schulze , Anton Mauder , Francisco Javier Santos Rodriguez
IPC分类号： H01L21/20
CPC分类号： H01L21/02658 , H01L21/76202 , H01L21/76224 , H01L29/8611 , Y10T428/218
摘要： A method for fabricating a porous semiconductor body region, comprising:producing at least one trench in a semiconductor body, starting from a surface of the semiconductor body, then producing at least one porous semiconductor body region in the semiconductor body starting from the at least one trench at least along a portion of the side walls of the trench, and then filling the trench with a semiconductor material (15) of the semiconductor body.
摘要翻译：一种制造多孔半导体体区域的方法，包括：从所述半导体本体的表面开始，在所述半导体本体中形成至少一个沟槽，然后在所述半导体本体中从所述至少一个沟槽，至少沿着沟槽的侧壁的一部分，然后用半导体本体的半导体材料（15）填充沟槽。

116. 发明申请

US20120223420A1 SEMICONDUCTOR BODY WITH A BURIED MATERIAL LAYER 审中-公开
标题翻译：半导体器件与一个材料层
公开(公告)号：US20120223420A1
公开(公告)日：2012-09-06
申请号：US13470830
申请日：2012-05-14
申请人： Hans-Joachim Schulze , Anton Mauder , Helmut Strack
发明人： Hans-Joachim Schulze , Anton Mauder , Helmut Strack
IPC分类号： H01L29/06
CPC分类号： H01L29/0649 , H01L21/0237 , H01L21/02642 , H01L21/02647 , H01L21/31144 , H01L21/74 , H01L21/76224 , H01L21/7624 , H01L21/76248 , H01L21/76283
摘要： One aspect includes a semiconductor arrangement with a semiconductor body having a first surface. A buried material layer is in the semiconductor body, the buried material layer being arranged distant to the first surface. A monocrystalline semiconductor material is arranged between the material layer and the first surface, and a monocrystalline semiconductor material adjoins the material layer in a lateral direction of the semiconductor body.
摘要翻译：一个方面包括具有半导体本体的具有第一表面的半导体装置。掩埋材料层位于半导体本体中，掩埋材料层被布置成远离第一表面。单晶半导体材料布置在材料层和第一表面之间，单晶半导体材料在半导体主体的横向方向上邻接材料层。

117. 发明申请

US20120018798A1 Method for Protecting a Semiconductor Device Against Degradation, a Semiconductor Device Protected Against Hot Charge Carriers and a Manufacturing Method Therefor 有权
标题翻译：用于保护半导体装置降解的方法，受热电荷载体保护的半导体装置及其制造方法
公开(公告)号：US20120018798A1
公开(公告)日：2012-01-26
申请号：US12843326
申请日：2010-07-26
申请人： Anton Mauder , Hans-Joachim Schulze
发明人： Anton Mauder , Hans-Joachim Schulze
IPC分类号： H01L29/78 , H01L21/336 , H01L29/06
CPC分类号： H01L29/407 , H01L21/283 , H01L29/063 , H01L29/0878 , H01L29/1608 , H01L29/2003 , H01L29/402 , H01L29/408 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/51 , H01L29/513 , H01L29/7393 , H01L29/7394 , H01L29/7397 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L29/792
摘要： A method for protecting a semiconductor device against degradation of its electrical characteristics is provided. The method includes providing a semiconductor device having a first semiconductor region and a charged dielectric layer which form a dielectric-semiconductor interface. The majority charge carriers of the first semiconductor region are of a first charge type. The charged dielectric layer includes fixed charges of the first charge type. The charge carrier density per area of the fixed charges is configured such that the charged dielectric layer is shielded against entrapment of hot majority charge carriers generated in the first semiconductor region. Further, a semiconductor device which is protected against hot charge carriers and a method for forming a semiconductor device are provided.
摘要翻译：提供了一种用于保护半导体器件免于其电特性劣化的方法。该方法包括提供具有形成介电半导体界面的第一半导体区域和带电介质层的半导体器件。第一半导体区域的多数电荷载流子是第一电荷类型。带电电介质层包括第一充电类型的固定电荷。固定电荷的每个面积的电荷载流子密度被配置为使得带电电介质层被屏蔽，以阻止在第一半导体区域中产生的热多数电荷载流子。此外，提供了防止热电荷载流子的半导体器件和形成半导体器件的方法。

118. 发明授权

US08089768B2 Component arragement with an optimized assembly capability 有权
标题翻译：具有优化装配能力的组件装配
公开(公告)号：US08089768B2
公开(公告)日：2012-01-03
申请号：US11659297
申请日：2005-07-14
申请人： Anton Mauder , Wolfgang Scholz
发明人： Anton Mauder , Wolfgang Scholz
IPC分类号： H05K7/20 , H01L23/36
CPC分类号： G02B6/4494 , G02B6/441 , H01L2924/0002 , H05K3/325 , H05K2201/10409 , H05K2201/10689 , H05K2201/2036 , H01L2924/00
摘要： The invention relates to a component arrangement. In at least one embodiment, the component arrangement comprises: an electronics module; a heat sink contacted by the electronics module; a printed circuit board, and; a fastening means for fastening the electronics module to the printed circuit board and to the heat sink. The electronics module has at least one elastic connecting limb for the solder-free contacting of the electronics module with the printed circuit board and has a location for the fastening means. The electronics module additionally comprises a decoupling means for decoupling the force of pressure between the connecting limb and the printed circuit board from the contact force between the heat sink and the electronics module. In at least one embodiment of the invention an electronics module is provided that can be used in the aforementioned component arrangement.
摘要翻译：本发明涉及一种组件装置。在至少一个实施例中，组件布置包括：电子模块; 由电子模块接触的散热器; 印刷电路板，以及用于将电子模块紧固到印刷电路板和散热器的紧固装置。电子模块具有至少一个弹性连接臂，用于电子模块与印刷电路板的无焊料接触并且具有紧固装置的位置。电子模块还包括用于将连接肢和印刷电路板之间的压力与散热器和电子模块之间的接触力分离的去耦装置。在本发明的至少一个实施例中，提供了可以用于上述部件布置的电子模块。

119. 发明授权

US07939850B2 Semiconductor device and method for producing a semiconductor device 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07939850B2
公开(公告)日：2011-05-10
申请号：US12403100
申请日：2009-03-12
申请人： Anton Mauder , Giulliano Aloise
发明人： Anton Mauder , Giulliano Aloise
IPC分类号： H01L29/74
CPC分类号： H01L29/861 , H01L29/0634
摘要： A semiconductor device has a semiconductor body with a semiconductor device structure including at least a first electrode and a second electrode. Between the two electrodes, a drift region is arranged, the drift region including charge compensation zones and drift zones arranged substantially parallel to one another. At least one charge carrier storage region which is at least partially free of charge compensation zones is arranged in the semiconductor body.
摘要翻译：半导体器件具有半导体器件结构，半导体器件结构至少包括第一电极和第二电极。在两个电极之间布置漂移区域，漂移区域包括电荷补偿区域和漂移区域彼此基本平行布置。至少部分没有电荷补偿区域的至少一个电荷载体存储区域被布置在半导体本体中。

120. 发明授权

US07916493B2 Power semiconductor module 有权
标题翻译：功率半导体模块
公开(公告)号：US07916493B2
公开(公告)日：2011-03-29
申请号：US11536384
申请日：2006-09-28
申请人： Friedrich Kroener , Anton Mauder
发明人： Friedrich Kroener , Anton Mauder
IPC分类号： H05K7/00
CPC分类号： H01L23/49833 , H01L23/3733 , H01L24/33 , H01L25/162 , H01L25/50 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/0102 , H01L2924/01029 , H01L2924/0103 , H01L2924/01032 , H01L2924/01033 , H01L2924/01038 , H01L2924/01041 , H01L2924/01044 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01056 , H01L2924/01057 , H01L2924/01058 , H01L2924/0106 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/30107 , H05K1/144 , H05K1/185 , H01L2924/00
摘要： A power semiconductor module has a controllable semiconductor chip (50), a first printed circuit board (1), a second printed circuit board (2), and also has one or a plurality of passive components (13, 18). The first printed circuit board (1) may have a conductor track structure (12, 13, 14), and the second printed circuit board (2) may have a conductor track structure (21, 22, 23, 24). Furthermore, an opening (19) in which the semiconductor chip (50) is arranged can be provided in the first printed circuit board (1). Furthermore, at least one passive component (13, 18) can be arranged on the first printed circuit board (1) or on the second printed circuit board (2).
摘要翻译：功率半导体模块具有可控半导体芯片（50），第一印刷电路板（1），第二印刷电路板（2），并且还具有一个或多个无源部件（13,18）。第一印刷电路板（1）可以具有导体轨道结构（12,13,14），并且第二印刷电路板（2）可以具有导体轨道结构（21,22,23,24）。此外，在第一印刷电路板（1）中可以设置有布置有半导体芯片（50）的开口（19）。此外，至少一个无源部件（13,18）可以布置在第一印刷电路板（1）上或第二印刷电路板（2）上。

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