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111. 发明申请

US20090194163A1 METHOD TO FORM A PHOTOVOLTAIC CELL COMPRISING A THIN LAMINA 审中-公开
公开(公告)号：US20090194163A1
公开(公告)日：2009-08-06
申请号：US12208298
申请日：2008-09-10
申请人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
发明人： Srinivasan Sivaram , Aditya Agarwal , S. Brad Herner , Christopher J. Petti
IPC分类号： H01L31/00
CPC分类号： H01L31/022425 , H01L31/0682 , H01L31/0747 , H01L31/1804 , H01L31/1892 , Y02E10/547 , Y02P70/521
摘要： A very thin photovoltaic cell is formed by implanting gas ions below the surface of a donor body such as a semiconductor wafer. Ion implantation defines a cleave plane, and a subsequent step exfoliates a thin lamina from the wafer at the cleave plane. A photovoltaic cell, or all or a portion of the base or emitter of a photovoltaic cell, is formed within the lamina. In preferred embodiments, the wafer is affixed to a receiver before the cleaving step. Electrical contact can be formed to both surfaces of the lamina, or to one surface only.

112. 发明授权

US07570523B2 Method for using two data busses for memory array block selection 有权
标题翻译：使用两个数据总线进行存储器阵列块选择的方法
公开(公告)号：US07570523B2
公开(公告)日：2009-08-04
申请号：US11461372
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
发明人： Roy E. Scheuerlein , Luca G. Fasoli , Christopher J. Petti
IPC分类号： G11C11/00
CPC分类号： G11C8/14 , G11C7/1048 , G11C7/18 , G11C8/08 , G11C8/12
摘要： Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and methods are described for selecting one or more array blocks of such a memory array, for selecting one or more word lines and bit lines within selected array blocks, for conveying data information to and from selected memory cells within selected array blocks, and for conveying unselected bias conditions to unselected array blocks.
摘要翻译：描述了用于解码可编程的示例性存储器阵列的电路和方法，在一些实施例中，可重写无源元件存储器单元，其对于具有多于一个存储器平面的非常密集的三维存储器阵列特别有用。此外，描述了用于选择这种存储器阵列的一个或多个阵列块的电路和方法，用于选择所选择的阵列块内的一个或多个字线和位线，用于将数据信息传送到选定的阵列块内的选定的存储器单元并且用于将未选择的偏置条件传送到未选择的阵列块。

113. 发明申请

US20090155962A1 Method for fabricating pitch-doubling pillar structures 有权
标题翻译：制造俯仰倍增柱结构的方法
公开(公告)号：US20090155962A1
公开(公告)日：2009-06-18
申请号：US12000758
申请日：2007-12-17
申请人： Christopher J. Petti , Steven J. Radigan
发明人： Christopher J. Petti , Steven J. Radigan
IPC分类号： H01L21/82
CPC分类号： H01L27/102 , H01L21/0337
摘要： A method of making a semiconductor device includes forming at least one device layer over a substrate, forming at least two spaced apart features over the at least one device layer, forming sidewall spacers on the at least two features, filling a space between a first sidewall spacer on a first feature and a second sidewall spacer on a second feature with a filler feature, selectively removing the sidewall spacers to leave the first feature, the filler feature and the second feature spaced apart from each other, and etching the at least one device layer using the first feature, the filler feature and the second feature as a mask.
摘要翻译：制造半导体器件的方法包括在衬底上形成至少一个器件层，在所述至少一个器件层上形成至少两个间隔开的特征，在所述至少两个特征上形成侧壁间隔物，填充第一侧壁第一特征上的间隔物和具有填充物特征的第二特征上的第二侧壁间隔物，选择性地移除侧壁间隔物以留下第一特征，填料特征和第二特征彼此间隔开，并且蚀刻至少一个装置层，使用第一特征，填充特征和第二特征作为掩模。

114. 发明申请

US20090003036A1 Method of making 3D R/W cell with reduced reverse leakage 有权
标题翻译：制造具有减少反向泄漏的3D R / W电池的方法
公开(公告)号：US20090003036A1
公开(公告)日：2009-01-01
申请号：US11819895
申请日：2007-06-29
申请人： Tanmay Kumar , Christopher J. Petti
发明人： Tanmay Kumar , Christopher J. Petti
IPC分类号： G11C11/34 , H01L21/02
CPC分类号： H01L27/101 , G11C13/00 , G11C13/0069 , G11C2013/009 , G11C2213/72 , H01L27/1021 , H01L27/24
摘要： A method of making a nonvolatile memory device includes forming a semiconductor diode steering element, and forming a semiconductor read/write switching element.
摘要翻译：制造非易失性存储器件的方法包括形成半导体二极管操控元件，以及形成半导体读/写开关元件。

115. 发明申请

US20080025061A1 HIGH BANDWIDTH ONE TIME FIELD-PROGRAMMABLE MEMORY 有权
标题翻译：高带宽一次性可编程存储器
公开(公告)号：US20080025061A1
公开(公告)日：2008-01-31
申请号：US11461410
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Christopher J. Petti
发明人： Roy E. Scheuerlein , Christopher J. Petti
IPC分类号： G11C17/00 , G11C11/00
CPC分类号： G11C8/06 , G11C5/145 , G11C5/147 , G11C7/12 , G11C8/08 , G11C8/12 , G11C11/5692 , G11C13/0023 , G11C13/0026 , G11C13/0028 , G11C13/003 , G11C13/0038 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2213/71 , G11C2213/72 , G11C2213/74
摘要： A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reverse bias operation that can reduce leakage currents through the array as well as decrease voltage levels that driver circuitry must normally produce in program operations. An array of memory cells can be fabricated by switching the memory cells from their initial virgin state to a second resistance state during the manufacturing process. In one embodiment, the factory switching operation can include popping an anti-fuse of each memory cell to set them into the second resistance state. The array of memory cells in the second resistance state are provided to an end-user. Control circuitry is also provided with the memory array that can switch the resistance of selected cells back toward their initial resistance state to program the array in accordance with data received from a user or host device.
摘要翻译：公开了具有相关制造和编程技术的一次性现场可编程（OTP）存储单元。根据一个实施例的OTP存储器单元包括与转向元件串联的至少一个电阻变化元件。使用反向偏置操作来对存储单元进行现场编程，该反向偏压操作可以减少通过阵列的漏电流，以及降低驱动器电路在程序运行中通常产生的电压电平。可以通过在制造过程中将存储器单元从其初始状态切换到第二电阻状态来制造存储器单元阵列。在一个实施例中，出厂切换操作可以包括弹出每个存储单元的反熔丝以使它们成为第二电阻状态。将第二电阻状态的存储单元的阵列提供给终端用户。控制电路还具有存储器阵列，其可以将所选择的单元的电阻切换回其初始电阻状态，以根据从用户或主机设备接收的数据对阵列进行编程。

116. 发明授权

US07272052B2 Decoding circuit for non-binary groups of memory line drivers 有权
标题翻译：用于非二进制组的存储器线路驱动器的解码电路
公开(公告)号：US07272052B2
公开(公告)日：2007-09-18
申请号：US11146952
申请日：2005-06-07
申请人： Roy E. Scheuerlein , Christopher J. Petti , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Christopher J. Petti , Luca G. Fasoli
IPC分类号： G11C16/06
CPC分类号： G11C8/10 , G11C5/063 , G11C8/08 , G11C8/14
摘要： A decoding circuit for non-binary groups of memory line drivers is disclosed. In one embodiment, an integrated circuit is disclosed comprising a binary decoder and circuitry operative to perform a non-binary arithmetic operation, wherein a result of the non-binary arithmetic operation is provided as input to the binary decoder. In another embodiment, an integrated circuit is disclosed comprising a memory array comprising a plurality of array lines, a non-integral-power-of-two number of array line driver circuits, and control circuitry configured to select one of the array line driver circuits. The control circuitry can comprise a binary decoder and a pre-decoder portion that performs a non-binary arithmetic operation. The concepts described herein may be used alone or in combination.
摘要翻译：公开了一种用于非二进制组的存储器线驱动器的解码电路。在一个实施例中，公开了一种集成电路，其包括二进制解码器和用于执行非二进制算术运算的电路，其中非二进制算术运算的结果被提供作为二进制解码器的输入。在另一个实施例中，公开了一种集成电路，其包括存储器阵列，该存储器阵列包括多个阵列线，两个非整数倍数量的阵列线驱动器电路，以及控制电路，被配置为选择阵列线驱动电路之一。控制电路可以包括执行非二进制算术运算的二进制解码器和预解码器部分。本文所述的概念可以单独使用或组合使用。

117. 发明授权

US07054219B1 Transistor layout configuration for tight-pitched memory array lines 有权
标题翻译：紧凑型内存阵列线的晶体管布局配置
公开(公告)号：US07054219B1
公开(公告)日：2006-05-30
申请号：US11095905
申请日：2005-03-31
申请人： Christopher J. Petti , Roy E. Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
发明人： Christopher J. Petti , Roy E. Scheuerlein , Tanmay Kumar , Abhijit Bandyopadhyay
IPC分类号： G11C8/00
CPC分类号： G11C8/14 , G11C5/02 , G11C5/063 , G11C8/08 , H01L27/0207 , H01L27/0688 , H01L27/10894 , H01L27/10897
摘要： A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontally across at least one memory block. Vertical active area stripes are disposed beneath a first memory block, and a respective plurality of bent-gate electrodes intersects each respective active area stripe to define individual source/drain regions. Every other source/drain region is coupled to a bias node for the active area stripe, and remaining source/drain regions are respectively coupled to a respective array line associated with the first memory block, thereby forming a respective first driver transistor for the respective array line.
摘要翻译：多头字线驱动电路包括弯栅晶体管，以减少为了与紧密排列的阵列线连接而实现的间距。在某些示例性实施例中，三维存储器阵列包括穿过至少一个存储器块水平横越的多个存储器块和阵列线。垂直有源区条纹设置在第一存储块下方，并且相应的多个弯曲栅电极与每个相应的有源区条纹相交以限定各个源/漏区。每个其它源极/漏极区域耦合到用于有源区域条纹的偏置节点，并且剩余的源极/漏极区域分别耦合到与第一存储器模块相关联的相应阵列线，从而形成用于相应阵列的相应的第一驱动器晶体管线。

118. 发明授权

US06992349B2 Rail stack array of charge storage devices and method of making same 有权
标题翻译：轨道堆叠阵列的电荷存储装置及其制作方法
公开(公告)号：US06992349B2
公开(公告)日：2006-01-31
申请号：US10849000
申请日：2004-05-20
申请人： Thomas H. Lee , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov
发明人： Thomas H. Lee , Andrew J. Walker , Christopher J. Petti , Igor G. Kouznetzov
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/14 , G11C16/26 , G11C16/3427 , G11C2211/5612 , H01L21/31053 , H01L21/76819 , H01L21/8221 , H01L23/528 , H01L23/5329 , H01L27/0688 , H01L27/112 , H01L27/11286 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11551 , H01L27/11556 , H01L27/11558 , H01L27/11565 , H01L27/11568 , H01L27/11573 , H01L27/11578 , H01L27/1158 , H01L27/12 , H01L27/1203 , H01L29/0626 , H01L29/0661 , H01L29/16 , H01L29/1604 , H01L29/42324 , H01L29/42332 , H01L29/42364 , H01L29/511 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66825 , H01L29/66833 , H01L29/7391 , H01L29/78642 , H01L29/7881 , H01L29/7889 , H01L29/792 , H01L29/7926 , H01L29/861 , H01L29/8616
摘要： There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.
摘要翻译：提供了一种包括多个器件级的电荷存储器件的单片三维阵列，其中通过化学机械抛光将两个连续的器件级之间的至少一个表面平坦化。

119. 发明授权

US06815781B2 Inverted staggered thin film transistor with salicided source/drain structures and method of making same 有权
标题翻译：具有水银源/漏极结构的反向交错薄膜晶体管及其制造方法
公开(公告)号：US06815781B2
公开(公告)日：2004-11-09
申请号：US10270394
申请日：2002-10-15
申请人： Michael A. Vyvoda , S. Brad Herner , Christopher J. Petti , Andrew J. Walker
发明人： Michael A. Vyvoda , S. Brad Herner , Christopher J. Petti , Andrew J. Walker
IPC分类号： H01L2975
CPC分类号： H01L27/0688 , H01L27/112 , H01L27/12
摘要： A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a second opening are located in the insulating fill layer, a first source or drain electrode is located in the first opening and a second source or drain electrode is located in the second opening. At least one of the first and the second source or drain electrodes comprise a polysilicon layer and a metal silicide layer.
摘要翻译：诸如倒置交错薄膜晶体管的半导体器件包括栅电极，位于栅电极上方的栅极绝缘层，位于栅极绝缘层上方的有源层和位于有源层上方的绝缘填充层。第一开口和第二开口位于绝缘填充层中，第一源极或漏极位于第一开口中，第二源极或漏极位于第二开口中。第一和第二源极或漏极中的至少一个包括多晶硅层和金属硅化物层。

120. 发明授权

US06501139B1 High-voltage transistor and fabrication process 有权
标题翻译：高压晶体管及制造工艺
公开(公告)号：US06501139B1
公开(公告)日：2002-12-31
申请号：US09823503
申请日：2001-03-30
申请人： Christopher J. Petti
发明人： Christopher J. Petti
IPC分类号： H01L2900
CPC分类号： H01L29/0653 , H01L21/26586 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L29/66659 , H01L29/7835
摘要： A high-voltage transistor and fabrication process in which the fabrication of the high-voltage transistor can be readily integrated into a conventional CMOS fabrication process. The high-voltage transistor of the invention includes a channel region formed beneath a portion of the gate electrode after the gate electrode has been formed on the surface of a semiconductor substrate. In a preferred embodiment, the channel region is formed by the angled ion implantation of dopant atoms using an edge of the gate electrode as a doping mask. The high-voltage transistor of the invention further includes a drain region that is spaced apart from the channel region by a portion of a well region and by an isolation region residing in the semiconductor substrate. By utilizing the process of the invention to fabricate the high-voltage transistor, the transistor can be integrated into an existing CMOS device with minimal allocation of additional substrate surface area.
摘要翻译：一种高压晶体管和制造工艺，其中高压晶体管的制造可以容易地集成到常规CMOS制造工艺中。本发明的高电压晶体管包括在栅极形成在半导体衬底的表面上之后形成在栅电极的一部分下方的沟道区。在优选实施例中，通过使用栅电极的边缘作为掺杂掩模的掺杂剂原子的成角度的离子注入形成沟道区。本发明的高压晶体管还包括漏极区域，其通过阱区域的一部分和位于半导体衬底中的隔离区域与沟道区域间隔开。通过利用本发明的方法制造高压晶体管，可以以最小的附加衬底表面积的分配将晶体管集成到现有的CMOS器件中。

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