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111. 发明授权

US08793544B2 Channel marking for chip mark overflow and calibration errors 有权
标题翻译：通道标记用于芯片标记溢出和校准错误
公开(公告)号：US08793544B2
公开(公告)日：2014-07-29
申请号：US12981017
申请日：2010-12-29
申请人： Judy S. Johnson , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
发明人： Judy S. Johnson , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/00 , G11C29/00 , G11C29/44 , G06F11/30 , G06F11/10
CPC分类号： G11C29/44 , G06F11/1044 , G06F11/1076 , G06F11/30 , G06F2211/1064
摘要： Marking memory chips as faulty when a fault is detected in data from the memory chip. Upon detecting that a plurality of memory chips are faulty, determining which of a plurality of memory channels contains the faulty memory chips. Marking one of a plurality of memory channels as failing in response to determining that the number of failing memory chips has exceeded a threshold.
摘要翻译：当从存储器芯片的数据中检测到故障时，将存储器芯片标记为故障。在检测到多个存储器芯片有故障时，确定多个存储器通道中的哪一个存储有故障的存储器芯片。响应于确定故障存储器芯片的数量已经超过阈值，将多个存储器通道中的一个标记为失败。

112. 发明授权

US08782485B2 Hierarchical channel marking in a memory system 有权
标题翻译：内存系统中的分层通道标记
公开(公告)号：US08782485B2
公开(公告)日：2014-07-15
申请号：US13353925
申请日：2012-01-19
申请人： Patrick J. Meaney , Eldee Stephens , Luis A. Lastras-Montano , Judy S. Johnson
发明人： Patrick J. Meaney , Eldee Stephens , Luis A. Lastras-Montano , Judy S. Johnson
IPC分类号： H03M13/00
CPC分类号： G06F11/1004 , G06F11/1076 , G06F2211/109 , H03M13/09 , H03M13/19 , H03M13/3715
摘要： Channel marking is provided in a memory system that includes a first memory channel, a second memory channel, and error correction code (ECC) logic. The memory system is configured to perform a method that includes receiving a request to apply a first channel mark to the first memory channel and determining a priority level of the first channel mark. A request is received to apply a second channel mark to the second memory channel, and a priority level of the second mark is determined. It is determined that the priority level of the first channel mark is higher than the priority level of the second channel mark. The first channel mark is supplied to the ECC logic while blocking the second channel mark from the ECC logic.
摘要翻译：在包括第一存储器通道，第二存储器通道和纠错码（ECC）逻辑的存储器系统中提供通道标记。存储器系统被配置为执行一种方法，该方法包括接收将第一信道标记应用于第一存储器信道并确定第一信道标记的优先级的请求。接收到将第二通道标记应用于第二存储器通道的请求，并且确定第二标记的优先级。确定第一通道标记的优先级高于第二通道标记的优先级。第一通道标记被提供给ECC逻辑，同时从ECC逻辑阻止第二通道标记。

113. 发明授权

US08553474B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08553474B2
公开(公告)日：2013-10-08
申请号：US13557294
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells.
摘要翻译：提供异构存储元件中的增加的容量，包括用于在异构存储器中存储数据的方法，该方法包括接收对应于其中至少两个存储器单元支持不同数据电平的存储器单元块的写入消息和写入地址，确定物理特性并且响应于物理特性识别与存储器单元块相关联的虚拟存储器。对每个虚拟存储器执行以下操作：生成描述虚拟存储器中的虚拟单元的约束向量; 以及响应于所述约束向量和所述写入数据计算虚拟写入向量，所述计算包括按顺序将所述写入数据逐位写入到所述虚拟存储器中，跳过已知被粘附到特定值的位置，如约束向量。虚拟写入向量被组合成写入字，并将写入字输出到存储器单元块。

114. 发明授权

US08499221B2 Accessing coded data stored in a non-volatile memory 有权
标题翻译：访问存储在非易失性存储器中的编码数据
公开(公告)号：US08499221B2
公开(公告)日：2013-07-30
申请号：US13556275
申请日：2012-07-24
申请人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
发明人： Michele M. Franceschini , Ashish Jagmohan , John P. Karidis , Luis A. Lastras-Montano
IPC分类号： G11C29/00
CPC分类号： G06F12/0246 , G06F11/1012 , G06F2212/1036 , G06F2212/401 , G06F2212/403 , G06F2212/7207 , G11C16/349
摘要： Adaptive endurance coding including a method for accessing memory that includes retrieving a codeword from a memory address. The codeword is multiplied by a metadata matrix to recover metadata for the codeword. The metadata includes a data location specification. The data in the codeword is identified in response to the metadata and the data is output as read data.
摘要翻译：适应性耐力编码包括用于访问存储器的方法，包括从存储器地址检索码字。将码字乘以元数据矩阵以恢复码字的元数据。元数据包括数据位置规范。代码字中的数据是响应于元数据而被识别的，数据被输出为读取数据。

115. 发明申请

US20130191685A1 PER-RANK CHANNEL MARKING IN A MEMORY SYSTEM 审中-公开
标题翻译：记忆系统中的全域通道标记
公开(公告)号：US20130191685A1
公开(公告)日：2013-07-25
申请号：US13353814
申请日：2012-01-19
申请人： Eldee Stephens , Patrick J. Meaney , Judy S. Johnson , Luis A. Lastras-Montano
发明人： Eldee Stephens , Patrick J. Meaney , Judy S. Johnson , Luis A. Lastras-Montano
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/085 , G06F11/1004 , G06F11/1076 , G06F2211/109
摘要： Channel marking is provided in a memory system that includes a memory channel with a plurality of memory devices. The memory devices are arranged into a first group of memory devices and a second group of memory devices. The memory system is configured to perform a method that includes determining that more than a threshold number of memory devices in the first group are failing. An error correction code (ECC) is configured to compensate for errors associated with memory devices in the first group on the memory channel and to perform error correction on errors associated with memory devices in the second group on the memory channel.
摘要翻译：在包括具有多个存储器件的存储器通道的存储器系统中提供通道标记。存储器件被布置成第一组存储器件和第二组存储器件。存储器系统被配置为执行包括确定第一组中多于一个阈值数量的存储器件失败的方法。错误校正码（ECC）被配置为补偿与存储器通道上的第一组中的存储器件相关联的错误，并且对与存储器通道上的第二组中的存储器件相关联的错误执行错误校正。

116. 发明授权

US08484529B2 Error correction and detection in a redundant memory system 有权
标题翻译：冗余存储器系统中的错误校正和检测
公开(公告)号：US08484529B2
公开(公告)日：2013-07-09
申请号：US12822503
申请日：2010-06-24
申请人： Luiz C. Alves , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens , Lisa C. Gower
发明人： Luiz C. Alves , Kevin C. Gower , Luis A. Lastras-Montano , Patrick J. Meaney , Eldee Stephens
IPC分类号： G06F11/00
CPC分类号： G06F11/1004 , G06F11/108
摘要： Error correction and detection in a redundant memory system that includes a memory controller; a plurality of memory channels in communication with the memory controller, the memory channels including a plurality of memory devices; a cyclical redundancy code (CRC) mechanism for detecting that one of the memory channels has failed, and for marking the memory channel as a failing memory channel; and an error correction code (ECC) mechanism. The ECC is configured for ignoring the marked memory channel and for detecting and correcting additional memory device failures on memory devices located on one or more of the other memory channels, thereby allowing the memory system to continue to run unimpaired in the presence of the memory channel failure.
摘要翻译：在包括存储器控制器的冗余存储器系统中的错误校正和检测; 与存储器控制器通信的多个存储器通道，存储器通道包括多个存储器件; 用于检测存储器通道之一的循环冗余码（CRC）机制已经失败，并用于将存储器通道标记为故障存储器通道; 和纠错码（ECC）机制。 ECC被配置为忽略标记的存储器通道并且用于检测和校正位于一个或多个其它存储器通道上的存储器设备上的附加存储器件故障，从而允许存储器系统在存在存储器通道的情况下继续运行不受损害失败。

117. 发明授权

US08261174B2 Protecting and migrating memory lines 失效
标题翻译：保护和迁移内存条
公开(公告)号：US08261174B2
公开(公告)日：2012-09-04
申请号：US12352744
申请日：2009-01-13
申请人： Luis A. Lastras-Montano
发明人： Luis A. Lastras-Montano
IPC分类号： G06F11/00
CPC分类号： H03M13/356 , G06F11/1012 , H03M13/15 , H03M13/1515
摘要： A data protection method is provided. The method includes receiving data; generating compressed data based on the data; determining a degree of compressibility based on the compressed data; determining an amount of free space based on the degree of compressibility; and setting one or more error bits based on the amount of free space.
摘要翻译：提供数据保护方法。该方法包括接收数据; 基于数据生成压缩数据; 基于压缩数据确定压缩程度; 基于可压缩程度确定自由空间的量; 并根据可用空间量设置一个或多个错误位。

118. 发明申请

US20120192034A1 Lengthening Life of a Limited Life Memory 有权
标题翻译：延长生命有限的生活记忆
公开(公告)号：US20120192034A1
公开(公告)日：2012-07-26
申请号：US13408407
申请日：2012-02-29
申请人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
IPC分类号： G11C29/00 , G06F11/08
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元矩阵。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息。

119. 发明授权

US08201069B2 Cyclical redundancy code for use in a high-speed serial link 失效
标题翻译：用于高速串行链路的循环冗余码
公开(公告)号：US08201069B2
公开(公告)日：2012-06-12
申请号：US12166207
申请日：2008-07-01
申请人： Timothy J. Dell , Kevin C. Gower , Luis A. Lastras-Montano
发明人： Timothy J. Dell , Kevin C. Gower , Luis A. Lastras-Montano
IPC分类号： G06F11/10 , H03M13/00
CPC分类号： H04L1/0056 , G06F11/10
摘要： A system and method for providing a cyclical redundancy code (CRC) for use in a high-speed serial link. The system includes a cascade interconnect memory system including a memory controller, a memory hub device and a downstream link. The downstream link is in communication with the memory controller and the memory hub device and includes at least thirteen signal lanes for transmitting a multiple transfer downstream frame from the memory controller to the memory hub device. A portion of the downstream frame includes downstream CRC bits to detect errors in the downstream frame. The downstream CRC bits capable of detecting any one of a lane failure, a transfer failure and up to five bit random errors.
摘要翻译：一种用于提供用于高速串行链路的循环冗余码（CRC）的系统和方法。该系统包括级联互连存储器系统，其包括存储器控制器，存储器集线器设备和下游链路。下游链路与存储器控制器和存储器集线器设备通信，并且包括用于将多个传输下行帧从存储器控制器发送到存储器集线器设备的至少十三个信号通道。下游帧的一部分包括用于检测下游帧中的错误的下行CRC位。下行CRC比特能够检测到车道故障，转移故障和高达五位随机错误中的任何一个。

120. 发明授权

US08099570B2 Methods, systems, and computer program products for dynamic selective memory mirroring 有权
标题翻译：用于动态选择性存储器镜像的方法，系统和计算机程序产品
公开(公告)号：US08099570B2
公开(公告)日：2012-01-17
申请号：US12035695
申请日：2008-02-22
申请人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
发明人： James A. O'Connor , Kanwal Bahri , Daniel J. Henderson , Luis A. Lastras-Montano , Warren E. Maule , Michael Mueller , Naresh Nayar , Richard Nicholas , Eric E. Retter , William J. Starke , Michael R. Trombley , Kenneth L. Wright
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F11/1666 , G06F11/1076 , G06F11/20 , G06F12/0246 , G06F2211/1088
摘要： Methods, systems, and computer program products are provided for dynamic selective memory mirroring in solid state devices. An amount of memory is reserved. Sections of the memory to select for mirroring in the reserved memory are dynamically determined. The selected sections of the memory contain critical areas. The selected sections of the memory are mirrored in the reserved memory.
摘要翻译：为固态设备中的动态选择性存储器镜像提供了方法，系统和计算机程序产品。保留一定量的内存。用于在保留的存储器中选择镜像的存储器的部分是动态确定的。存储器的选定部分包含关键区域。存储器的选定部分被镜像在保留的存储器中。

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