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1. 发明申请

US20100218070A1 LENGTHENING LIFE OF A LIMITED LIFE MEMORY 有权
标题翻译：延长有限生命记忆的寿命
公开(公告)号：US20100218070A1
公开(公告)日：2010-08-26
申请号：US12391547
申请日：2009-02-24
申请人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
IPC分类号： H03M13/00 , G11C11/00 , G11C7/00 , G06F11/00 , G06F11/16
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells, including at least a first group with at least one cell. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way (the cells can be PCM or another technology). Each one of the storage cells is arbitrarily individually changeable among the at least two levels, and each of the cells is cost-asymmetric. A controller encodes the identical message in the at least first group using the first way or the second way, based on which way incurs a least cost when writing the message into the at least one cell of the at least first group, given current levels of the at least first group.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元的矩阵，包括至少一个具有至少一个单元的第一组。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息（该单元可以是PCM或另一种技术）。存储单元中的每一个在至少两个级别中可任意地单独变化，并且每个单元是成本不对称的。控制器使用第一种方法或第二种方式在至少第一组中编码相同的消息，基于哪种方式在将消息写入至少第一组的至少一个小区时产生最低成本，给定当前级别至少第一组。

2. 发明申请

US20120192034A1 Lengthening Life of a Limited Life Memory 有权
标题翻译：延长生命有限的生活记忆
公开(公告)号：US20120192034A1
公开(公告)日：2012-07-26
申请号：US13408407
申请日：2012-02-29
申请人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
IPC分类号： G11C29/00 , G06F11/08
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元矩阵。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息。

3. 发明授权

US08413004B2 Lengthening life of a limited life memory 有权
标题翻译：延长生命有限的生活记忆
公开(公告)号：US08413004B2
公开(公告)日：2013-04-02
申请号：US13408407
申请日：2012-02-29
申请人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
发明人： Michele Franceschini , John Peter Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mark N. Wegman
IPC分类号： G08C25/02 , H04L1/18 , H04H40/00 , H04W4/00 , H04W24/00 , H04B7/00 , G11C11/34 , G11C16/04 , G06M3/00
CPC分类号： G11C13/0069 , G06F11/1012 , G11C13/0002 , G11C2207/104
摘要： A phase-change memory (PCM) includes a matrix of storage cells, including at least a first group with at least one cell. Each cell includes a phase change material having at least a first resistance value and a second resistance value, such that the first group can have an identical message encoded therein in at least a first way and a second way. The memory also includes a controller configured to encode the identical message in the at least first group the first or second way, based on which way causes the least amount of writing cost, given current levels of the group. Another embodiment of memory includes a matrix of storage cells. Each of the storage cells has at least two levels, such that each of the storage cells can have an identical message encoded therein in at least a first way and a second way.
摘要翻译：相变存储器（PCM）包括存储单元矩阵，至少包括具有至少一个单元的第一组。每个单元包括具有至少第一电阻值和第二电阻值的相变材料，使得第一组可以以至少第一种方式和第二种方式在其中编码相同的消息。所述存储器还包括控制器，所述控制器被配置为在所述至少第一组中对所述第一或第二方式的相同消息进行编码，基于哪种方式，给出所述组的当前级别的最小写入成本量。存储器的另一实施例包括存储单元矩阵。每个存储单元具有至少两个级别，使得每个存储单元可以以至少第一种方式和第二种方式在其中编码相同的消息。

4. 发明授权

US08488397B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08488397B2
公开(公告)日：2013-07-16
申请号：US13557298
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for reading from memory. The method includes receiving a read word from a block of memory cells, where physical characteristics of the memory cells support different sets of data levels. The read word is separated into two or more virtual read vectors. For each of the virtual read vectors, the codebook that was utilized to generate the virtual read vector is identified and a partial read data vector is generated. The generating includes multiplying the virtual read vector by a matrix that represents the codebook. The partial read data vectors are combined into a read message and the read message is output.
摘要翻译：在异构存储元件中提供增加的容量，包括从存储器读取的方法。该方法包括从存储器单元块接收读取字，其中存储器单元的物理特性支持不同数据级的集合。读取的字被分成两个或更多个虚拟读取向量。对于每个虚拟读取向量，识别用于生成虚拟读取向量的码本，并生成部分读取数据向量。生成包括将虚拟读取向量乘以代表码本的矩阵。将部分读取数据矢量组合成读取消息，并输出读出的消息。

5. 发明授权

US08331168B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08331168B2
公开(公告)日：2012-12-11
申请号：US12433157
申请日：2009-04-30
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.
摘要翻译：提供异构存储元件的增加的容量，包括用于存储数据的方法，包括对存储器的写入过程写入和从存储器读取读取过程。存储器单元的物理特性在存储器中支持不同的数据级别。写入过程在写入存储器时考虑到不同的数据级别集。读取过程首先获得存储器中的数据，然后确定如何解释数据。

6. 发明授权

US08553474B2 Increased capacity heterogeneous storage elements 有权
标题翻译：增加容量的异构存储元件
公开(公告)号：US08553474B2
公开(公告)日：2013-10-08
申请号：US13557294
申请日：2012-07-25
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data in a heterogeneous memory that includes receiving a write message and a write address corresponding to a block of memory cells where at least two of the memory cells support different data levels, determining physical characteristics of the memory cells, and identifying virtual memories associated with the block of memory cells in response to the physical characteristics. The following is performed for each of the virtual memories: generating a constraint vector that describes the virtual cells in the virtual memory; and calculating a virtual write vector in response to the constraint vector and the write data, the calculating including writing the write data, bit by bit, in order, into the virtual memory, skipping locations known to be stuck to a particular value as indicated by the constraint vector. The virtual write vectors are combined into a write word and the write word is output to the block of memory cells.
摘要翻译：提供异构存储元件中的增加的容量，包括用于在异构存储器中存储数据的方法，该方法包括接收对应于其中至少两个存储器单元支持不同数据电平的存储器单元块的写入消息和写入地址，确定物理特性并且响应于物理特性识别与存储器单元块相关联的虚拟存储器。对每个虚拟存储器执行以下操作：生成描述虚拟存储器中的虚拟单元的约束向量; 以及响应于所述约束向量和所述写入数据计算虚拟写入向量，所述计算包括按顺序将所述写入数据逐位写入到所述虚拟存储器中，跳过已知被粘附到特定值的位置，如约束向量。虚拟写入向量被组合成写入字，并将写入字输出到存储器单元块。

7. 发明申请

US20100277989A1 INCREASED CAPACITY HETEROGENEOUS STORAGE ELEMENTS 有权
标题翻译：增加容量异质存储元素
公开(公告)号：US20100277989A1
公开(公告)日：2010-11-04
申请号：US12433157
申请日：2009-04-30
申请人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
发明人： Ibrahim M. Elfadel , Michele Franceschini , Ashish Jagmohan , Luis A. Lastras-Montano , Mayank Sharma
IPC分类号： G11C7/00
CPC分类号： G11C29/08 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0076 , G11C2211/5641
摘要： Providing increased capacity in heterogeneous storage elements including a method for storing data including a write process writing to a memory and a read process reading from the memory. Physical characteristics of memory cells in the memory support different sets of data levels. The write process takes into account the different sets of data levels when writing to the memory. The read process first obtains data in the memory and subsequently determines how to interpret the data.
摘要翻译：提供异构存储元件的增加的容量，包括用于存储数据的方法，包括对存储器的写入过程写入和从存储器读取读取过程。存储器单元的物理特性在存储器中支持不同的数据级别。写入过程在写入存储器时考虑到不同的数据级别集。读取过程首先获得存储器中的数据，然后确定如何解释数据。

8. 发明授权

US08897062B2 Memory programming for a phase change memory cell 有权
标题翻译：相变存储单元的存储器编程
公开(公告)号：US08897062B2
公开(公告)日：2014-11-25
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00 , G11C13/00 , G11C29/02
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

9. 发明申请

US20110228600A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20110228600A1
公开(公告)日：2011-09-22
申请号：US13150690
申请日：2011-06-01
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/21
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

10. 发明申请

US20100214829A1 MEMORY PROGRAMMING 有权
标题翻译：内存编程
公开(公告)号：US20100214829A1
公开(公告)日：2010-08-26
申请号：US12391693
申请日：2009-02-24
申请人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
发明人： Matthew J. Breitwisch , Roger W. Cheek , Stefanie R. Chiras , Ibrahim M. Elfadel , Michele M. Franceschini , John P. Karidis , Luis A. Lastras-Montano , Thomas Mittelholzer , Mayank Sharma
IPC分类号： G11C11/00
CPC分类号： G11C29/02 , G11C13/0004 , G11C13/0064 , G11C13/0069 , G11C29/021 , G11C29/028 , G11C2013/0092
摘要： Systems, methods, and devices for iteratively writing contents to memory locations are provided. A statistical model is used to determine a sequence of pulses to write desired contents to a memory location. The contents can be expressed as a resistance value in a range to store one or more bits in a memory cell. For phase change memory, an adaptive reset pulse and one or more annealing pulses are selected based on a desired resistance range. Reading the resistance value of the memory cell can provide feedback to determine adjustments in an overall pulse application strategy. The statistical model and a look up table can be used to select and modify pulses. Adaptively updating the statistical model and look up table may reduce the number of looping iterations to shift the resistance value of the memory cell into the desired resistance range.
摘要翻译：提供了用于向内存位置迭代地写入内容的系统，方法和设备。统计模型用于确定将所需内容写入存储器位置的脉冲序列。内容可以表示为在存储单元中存储一个或多个位的范围内的电阻值。对于相变存储器，基于期望的电阻范围来选择自适应复位脉冲和一个或多个退火脉冲。读取存储器单元的电阻值可提供反馈以确定整体脉冲应用策略中的调整。统计模型和查询表可用于选择和修改脉冲。自适应地更新统计模型和查找表可以减少循环迭代的次数以将存储器单元的电阻值移动到期望的电阻范围。

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