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111. 发明授权

US07138685B2 Vertical MOSFET SRAM cell 失效
标题翻译：垂直MOSFET SRAM单元
公开(公告)号：US07138685B2
公开(公告)日：2006-11-21
申请号：US10318495
申请日：2002-12-11
申请人： Louis L. Hsu , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
发明人： Louis L. Hsu , Oleg Gluschenkov , Jack A. Mandelman , Carl J. Radens
IPC分类号： H01L21/00
CPC分类号： H01L27/11 , G11C11/412 , H01L21/84 , H01L27/1104 , H01L27/1203
摘要： A method of forming an SRAM cell device includes the following steps. Form pass gate FET transistors and form a pair of vertical pull-down FET transistors with a first common body and a first common source in a silicon layer patterned into parallel islands formed on a planar insulator. Etch down through upper diffusions between cross-coupled inverter FET transistors to form pull-down isolation spaces bisecting the upper strata of pull-up and pull-down drain regions of the pair of vertical pull-down FET transistors, with the isolation spaces reaching down to the common body strata. Form a pair of vertical pull-up FET transistors with a second common body and a second common drain. Then, connect the FET transistors to form an SRAM cell.
摘要翻译：形成SRAM单元装置的方法包括以下步骤。形成栅极FET晶体管并形成一对垂直下拉FET晶体管，其具有第一共同体和第一公共源，图案化为平坦绝缘体上形成平行岛的硅层。通过交叉耦合的反相器FET晶体管之间的上扩散来蚀刻，以形成将一对垂直下拉FET晶体管的上拉和下拉漏极区的上层平分的下拉隔离空间，隔离空间达到到共同的身体层。形成一对具有第二共同体和第二公共漏极的垂直上拉FET晶体管。然后，连接FET晶体管以形成SRAM单元。

112. 发明授权

US07084024B2 Gate electrode forming methods using conductive hard mask 失效
标题翻译：使用导电硬掩模的栅电极形成方法
公开(公告)号：US07084024B2
公开(公告)日：2006-08-01
申请号：US10711642
申请日：2004-09-29
申请人： Oleg Gluschenkov , Dae-Gyu Park
发明人： Oleg Gluschenkov , Dae-Gyu Park
IPC分类号： H01L21/8238
CPC分类号： H01L21/28079 , H01L21/32139 , H01L21/823842 , H01L29/4958 , H01L29/517 , H01L29/518
摘要： Methods related to formation of a gate electrode are disclosed that employ a conductive hard mask as a protective layer during a photoresist removal process. In preferred embodiments, the conductive hard mask includes a metal containing conductor or a metal silicide. The invention prevents process damage on the gate dielectric during wet and/or dry resist strip, and since the conductive hard mask cannot be etched in typical resist strip chemistries, the invention also protects a metal electrode under the hard mask. The steps disclosed allow creation of a multiple work function metal gate electrode, or a mixed metal and polysilicon gate electrode, which do not suffer from the problems of the related art.
摘要翻译：公开了在光致抗蚀剂去除过程中使用导电硬掩模作为保护层的与栅电极的形成有关的方法。在优选实施例中，导电硬掩模包括含金属的导体或金属硅化物。本发明防止了在湿式和/或干式抗蚀剂条带期间对栅极电介质的工艺损伤，并且由于导电硬掩模不能在典型的抗蚀剂条纹化学中被蚀刻，本发明还保护硬掩模下面的金属电极。所公开的步骤允许创建不具有现有技术问题的多功能金属栅电极或混合金属和多晶硅栅电极。

113. 发明申请

US20060105516A1 Oxidation method for altering a film structure 失效
标题翻译：用于改变膜结构的氧化方法
公开(公告)号：US20060105516A1
公开(公告)日：2006-05-18
申请号：US11318818
申请日：2005-12-27
申请人： Michael Belyansky , Diane Boyd , Bruce Doris , Oleg Gluschenkov
发明人： Michael Belyansky , Diane Boyd , Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L21/8238
CPC分类号： H01L29/7843 , H01L21/823807 , H01L21/823814 , H01L21/84 , H01L27/1203
摘要： A method is provided in which a stress present in a film is reduced in magnitude by oxidizing the film through atomic oxygen supplied to a surface of the film. In an embodiment, a mask is used to selectively block portions of the film so that the stress is relaxed only in areas exposed to the oxidation process. A method is further provided in which a film having a stress is formed over source and drain regions of an NFET and a PFET. The stress present in the film over the source and drain regions of either the NFET or the PFET is then relaxed by oxidizing the film through exposure to atomic oxygen to provide enhanced mobility in at least one of the NFET or the PFET while maintaining desirable mobility in the other of the NFET and PFET.
摘要翻译：提供了一种方法，其中通过供应到膜的表面的原子氧氧化膜来减小膜中存在的应力。在一个实施例中，掩模用于选择性地阻挡膜的部分，使得应力仅在暴露于氧化过程的区域中松弛。还提供了一种方法，其中在NFET和PFET的源极和漏极区域上形成具有应力的膜。然后在NFET或PFET的源极和漏极区域上存在于膜中的应力通过暴露于原子氧氧化膜而被松弛，以在至少一个NFET或PFET中提供增强的迁移率，同时保持理想的迁移率另一个是NFET和PFET。

114. 发明申请

US20060076627A1 ULTRA SHALLOW JUNCTION FORMATION BY EPITAXIAL INTERFACE LIMITED DIFFUSION 有权
标题翻译：通过外延界面有限扩散形成的超声结构
公开(公告)号：US20060076627A1
公开(公告)日：2006-04-13
申请号：US10711899
申请日：2004-10-12
申请人： Huajie Chen , Omer Dokumaci , Oleg Gluschenkov , Werner Rausch
发明人： Huajie Chen , Omer Dokumaci , Oleg Gluschenkov , Werner Rausch
IPC分类号： H01L29/94
CPC分类号： H01L21/26533 , H01L21/02238 , H01L21/26513 , H01L21/31654 , H01L21/31675 , H01L21/324 , H01L29/0847 , H01L29/66636
摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.
摘要翻译：形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。更具体地，本发明增加了硅衬底的顶表面的氧含量。优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。这允许本发明在硅衬底的顶表面上外延生长硅层。此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

115. 发明授权

US07023064B2 Temperature stable metal nitride gate electrode 有权
标题翻译：温度稳定的金属氮化物栅电极
公开(公告)号：US07023064B2
公开(公告)日：2006-04-04
申请号：US10710063
申请日：2004-06-16
申请人： Dae-Gyu Park , Cyril Cabral, Jr. , Oleg Gluschenkov , Hyungjun Kim
发明人： Dae-Gyu Park , Cyril Cabral, Jr. , Oleg Gluschenkov , Hyungjun Kim
IPC分类号： H01L29/76
CPC分类号： H01L21/823842 , H01L21/823857 , Y10S257/90 , Y10S438/942
摘要： An integrated circuit is provided including an FET gate structure formed on a substrate. This structure includes a gate dielectric on the substrate, and a metal nitride layer overlying the gate dielectric and in contact therewith. This metal nitride layer is characterized as MNx, where M is one of W, Re, Zr, and Hf, and x is in the range of about 0.7 to about 1.5. Preferably the layer is of WNx, and x is about 0.9. Varying the nitrogen concentration in the nitride layer permits integration of different FET characteristics on the same chip. In particular, varying x in the WNx layer permits adjustment of the threshold voltage in the different FETs. The polysilicon depletion effect is substantially reduced, and the gate structure can be made thermally stable up to about 1000° C.
摘要翻译：提供了一种集成电路，其包括形成在衬底上的FET栅极结构。该结构包括衬底上的栅极电介质和覆盖栅极电介质并与其接触的金属氮化物层。该金属氮化物层的特征在于MN x，其中M是W，Re，Zr和Hf之一，x在约0.7至约1.5的范围内。优选地，该层为W N x X，x为约0.9。改变氮化物层中的氮浓度允许在同一芯片上集成不同的FET特性。特别地，在WN 层中改变x允许调节不同FET中的阈值电压。多晶硅耗尽效应显着降低，并且栅极结构可以在高达约1000℃下热稳定。

116. 发明申请

US20060027868A1 High mobility CMOS circuits 有权
标题翻译：高移动性CMOS电路
公开(公告)号：US20060027868A1
公开(公告)日：2006-02-09
申请号：US11244291
申请日：2005-10-06
申请人： Bruce Doris , Oleg Gluschenkov , Huilong Zhu
发明人： Bruce Doris , Oleg Gluschenkov , Huilong Zhu
IPC分类号： H01L27/12
CPC分类号： H01L29/7842 , H01L21/823807 , H01L21/823828
摘要： Semiconductor structure formed on a substrate and process of forming the semiconductor. The semiconductor includes a plurality of field effect transistors having a first portion of field effect transistors (FETS) and a second portion of field effect transistors. A first stress layer has a first thickness and is configured to impart a first determined stress to the first portion of the plurality of field effect transistors. A second stress layer has a second thickness and is configured to impart a second determined stress to the second portion of the plurality of field effect transistors.
摘要翻译：在衬底上形成的半导体结构和形成半导体的工艺。半导体包括具有场效应晶体管（FETS）的第一部分和场效应晶体管的第二部分的多个场效应晶体管。第一应力层具有第一厚度并且被配置为向多个场效应晶体管的第一部分施加第一确定的应力。第二应力层具有第二厚度，并且被配置为将第二确定的应力赋予多个场效应晶体管的第二部分。

117. 发明申请

US20050264320A1 LOGIC CIRCUITS HAVING LINEAR AND CELLULAR GATE TRANSISTORS 失效
标题翻译：具有线性和细胞栅极晶体管的逻辑电路
公开(公告)号：US20050264320A1
公开(公告)日：2005-12-01
申请号：US10709784
申请日：2004-05-27
申请人： Victor Chan , Hsing-Jen Wann , Shih-Fen Huang , Oleg Gluschenkov
发明人： Victor Chan , Hsing-Jen Wann , Shih-Fen Huang , Oleg Gluschenkov
IPC分类号： H01L27/02 , H03K17/16 , H03K19/017 , H03K19/094 , H03K19/0948
CPC分类号： H03K19/0948 , H01L27/0203 , H03K19/01707
摘要： A logic circuit is provided with a first inverter having a plurality of linear gate transistors driving a first capacitive load and a second inverter having a plurality of cellular gate transistors driving a second capacitive load. The first inverter is serially connected to the second inverter. The second capacitive load is larger than the first capacitive load.
摘要翻译：逻辑电路设置有具有驱动第一电容性负载的多个线性栅极晶体管的第一反相器和驱动第二电容负载的多个蜂窝状栅极晶体管的第二反相器。第一个逆变器串联连接到第二个逆变器。第二容性负载大于第一容性负载。

118. 发明授权

US06960514B2 Pitcher-shaped active area for field effect transistor and method of forming same 失效
标题翻译：投币型场效应晶体管及其形成方法
公开(公告)号：US06960514B2
公开(公告)日：2005-11-01
申请号：US10803395
申请日：2004-03-18
申请人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
发明人： Jochen Beintner , Rama Divakaruni , Johnathan Faltermeier , Philip L. Flaitz , Oleg Gluschenkov , Carol J. Heenan , Rajarao Jammy , Byeong Kim , Mihel Seitz , Akira Sudo , Yoichi Takegawa
IPC分类号： H01L21/762
CPC分类号： H01L21/76224
摘要： An improved pitcher-shaped active area for a field effect transistor that, for a given gate length, achieves an increase in transistor on-current, a decrease in transistor serial resistance, and a decrease in contact resistance. The pitcher-shaped active area structure includes at least two shallow trench insulator (STI) structures formed into a substrate that defines an active area structure, which includes a widened top portion with a larger width than a bottom portion. An improved fabrication method for forming the improved pitcher-shaped active area is also described that implements a step to form STI structure divots followed by a step to migrate substrate material into at least portions of the divots, thereby forming a widened top portion of the active area structure. The fabrication method of present invention forms the pitcher-shaped active area without the use of lithography, and therefore, is not limited by the smallest ground rules of lithography tooling.
摘要翻译：对于给定的栅极长度，对于晶体管导通电流的增加，晶体管串联电阻的降低和接触电阻的降低，用于场效应晶体管的改进的投池形有源区域。投球形有源区结构包括形成在衬底中的至少两个浅沟槽绝缘体（STI）结构，其限定有源区域结构，其包括宽度比底部宽的加宽顶部部分。还描述了一种用于形成改进的捕鱼器活性区域的改进的制造方法，其实现了形成STI结构图形的步骤，随后是将基板材料迁移到图案的至少部分中的步骤，从而形成活动的加宽顶部区域结构。本发明的制造方法在不使用光刻的情况下形成投手型有源区域，因此不受光刻工具的最小基准规则的限制。

119. 发明申请

US20050189589A1 HYBRID SOI/BULK SEMICONDUCTOR TRANSISTORS 有权
标题翻译：混合SOI / BULK半导体晶体管
公开(公告)号：US20050189589A1
公开(公告)日：2005-09-01
申请号：US10708378
申请日：2004-02-27
申请人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
发明人： Huilong Zhu , Philip Oldiges , Bruce Doris , Xinlin Wang , Oleg Gluschenkov , Huajie Chen , Ying Zhang
IPC分类号： H01L27/01 , H01L29/06 , H01L29/10 , H01L29/786
CPC分类号： H01L29/7849 , H01L29/0653 , H01L29/1054 , H01L29/7842 , H01L29/78603 , H01L29/78612 , H01L29/78618 , H01L29/78687
摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.
摘要翻译：场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。携带者的流动性可能会与其他有利的影响相结合。

120. 发明申请

US20050148146A1 High performance strained CMOS devices 失效
标题翻译：高性能应变CMOS器件
公开(公告)号：US20050148146A1
公开(公告)日：2005-07-07
申请号：US11060784
申请日：2005-02-18
申请人： Bruce Doris , Oleg Gluschenkov
发明人： Bruce Doris , Oleg Gluschenkov
IPC分类号： H01L20060101 , H01L21/336 , H01L21/76 , H01L21/8238 , H01L29/78
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823878 , H01L29/66575 , H01L29/78 , H01L29/7846
摘要： A semiconductor device and method of manufacture provide an n-channel field effect transistor (nFET) having a shallow trench isolation with overhangs that overhang Si—SiO2 interfaces in a direction parallel to the direction of current flow and in a direction transverse to current flow. The device and method also provide a p-channel field effect transistor (pFET) having a shallow trench isolation with an overhang that overhangs Si—SiO2 interfaces in a direction transverse to current flow. However, the shallow trench isolation for the pFET is devoid of overhangs, in the direction parallel to the direction of current flow.
摘要翻译：一种半导体器件和制造方法提供一种具有浅沟槽隔离的n沟道场效应晶体管（nFET），其具有在与电流流动方向平行的方向上突出Si-SiO 2界面; 在横向于电流的方向上。器件和方法还提供具有浅沟槽隔离的p沟道场效应晶体管（pFET），其具有在横向于电流的方向上突出Si-SiO 2界面的突出端。然而，pFET的浅沟槽隔离在平行于电流方向的方向上没有突出端。

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