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111. 发明授权

US06696865B2 Semiconductor integrated circuit device having power reduction mechanism 失效
标题翻译：具有功率降低机构的半导体集成电路装置
公开(公告)号：US06696865B2
公开(公告)日：2004-02-24
申请号：US10283280
申请日：2002-10-30
申请人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
发明人： Masashi Horiguchi , Kunio Uchiyama , Kiyoo Itoh , Takeshi Sakata , Masakazu Aoki , Takayuki Kawahara
IPC分类号： H03K19094
CPC分类号： H01L27/0207 , G06F1/3203 , G11C5/14 , H01L27/0218 , H03K3/356113 , H03K19/0013 , H03K19/0016 , H03K19/01721
摘要： A semiconductor integrated circuit device is composed of logic gates each provided with at least two MOS transistors. The logic gates are connected to a first potential point and a second potential point. The substrate voltages of the transistors are set so that the threshold voltage would be varied based on the operation mode. The semiconductor integrated circuit device includes a current control device connected between the logic gate and the first potential point and/or between the logic gate and the second potential point for controlling a value of a current flowing in the logic gate depending on an operating state of the logic gate. The circuit can be used in devices that cycle in operation between high and low power consumption modes, such as microprocessors that have both an operation mode and a low power back-up or sleep mode used for power reduction.
摘要翻译：半导体集成电路器件由各自设置有至少两个MOS晶体管的逻辑门组成。逻辑门连接到第一电势点和第二电位点。晶体管的衬底电压被设置为使得阈值电压将基于操作模式而改变。半导体集成电路装置包括连接在逻辑门与第一电位点之间和/或逻辑门与第二电势点之间的电流控制装置，用于根据操作状态控制在逻辑门中流动的电流的值逻辑门。该电路可用于在高功耗模式和低功耗模式之间循环运行的器件，例如具有用于功率降低的操作模式和低功率备用或睡眠模式的微处理器。

112. 发明授权

US06630731B2 Semiconductor device 有权
公开(公告)号：US06630731B2
公开(公告)日：2003-10-07
申请号：US10050951
申请日：2002-01-22
申请人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
发明人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
IPC分类号： H01L25065
CPC分类号： H01L24/50 , H01L23/49572 , H01L23/49816 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L27/10897 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/16245 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2225/1029 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12033 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2924/3511 , H01L2924/00015 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

113. 发明授权

US06492719B2 Semiconductor device 有权
公开(公告)号：US06492719B2
公开(公告)日：2002-12-10
申请号：US09984089
申请日：2001-10-26
申请人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
发明人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
IPC分类号： H01L25065
CPC分类号： H01L24/50 , H01L23/49572 , H01L23/49816 , H01L24/06 , H01L24/45 , H01L24/48 , H01L25/0657 , H01L25/105 , H01L27/10897 , H01L2224/0401 , H01L2224/04042 , H01L2224/06136 , H01L2224/16245 , H01L2224/451 , H01L2224/45144 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2225/1029 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01021 , H01L2924/01024 , H01L2924/01029 , H01L2924/01033 , H01L2924/0105 , H01L2924/01055 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/12033 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/15312 , H01L2924/15331 , H01L2924/181 , H01L2924/19041 , H01L2924/3011 , H01L2924/3511 , H01L2924/00015 , H01L2224/05599 , H01L2924/00 , H01L2924/00012
摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

114. 发明授权

US06473354B2 Semiconductor integrated circuit device and method of activating the same 有权
公开(公告)号：US06473354B2
公开(公告)日：2002-10-29
申请号：US10040492
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.

115. 发明授权

US06424590B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06424590B1
公开(公告)日：2002-07-23
申请号：US10023891
申请日：2001-12-21
申请人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C800
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instructions for the memory unit is provided, the data input buffer is rendered active in advance before the instructions for the write operation is provided, whereby wastefully consumed power is reduced.
摘要翻译：在具有能够向每个存储单元输入写入数据的数据输入缓冲器的半导体器件中，在接收到对存储器单元进行的写入操作的指令之后，数据输入缓冲器从非活动状态改变为有效状态。数据输入缓冲器是具有例如基于SSTL的接口规格的差分输入缓冲器，其通过接通电源开关而进入活动状态，从而使通过电流流过并在其中立即接收信号小振幅信号的小变化。由于输入缓冲器仅在提供存储单元的写入操作指令时才进入活动状态，所以在提供用于写入操作的指令之前，数据输入缓冲器被预先激活，从而减少浪费的功率。

116. 发明授权

US06424586B1 Semiconductor integrated circuit device and method of activating same 有权
标题翻译：半导体集成电路器件及其激活方法
公开(公告)号：US06424586B1
公开(公告)日：2002-07-23
申请号：US10040435
申请日：2002-01-09
申请人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
发明人： Hiromasa Noda , Masakazu Aoki , Youji Idei , Kazuhiko Kajigaya , Osamu Nagashima , Kiyoo Itoh , Masashi Horiguchi , Takeshi Sakata
IPC分类号： G11C700
CPC分类号： G11C5/14 , G11C5/147 , G11C11/4074 , H03K19/0016
摘要： A dynamic RAM is divided into an input circuit block responsive to an input signal supplied from an external terminal, inclusive of an operation start signal, an internal circuit block activated in response to the signal inputted from the input circuit block, and an output circuit block for outputting a signal outputted from the internal circuit block to an external terminal. A plurality of switch MOSFETs are provided in parallel form between a power line for applying an operating voltage supplied from an external terminal and an internal power line for a first circuit portion in the internal circuit block, which does not need a storage operation upon its non-operating state. Further, the switch MOSFETs are stepwise turned on in response to controls signals produced by delaying a start signal supplied through the input circuit block in turn, so as to perform the supply of each operating voltage.
摘要翻译：动态RAM被分成响应于从外部端子提供的输入信号的输入电路块，包括操作开始信号，响应于从输入电路块输入的信号而被激活的内部电路块，以及输出电路块用于将从内部电路块输出的信号输出到外部端子。在用于施加从外部端子提供的工作电压的电力线和用于内部电路块中的第一电路部分的内部电力线之间的并行形式提供多个开关MOSFET，其不需要在其非正常状态下的存储操作操作状态。此外，响应于通过延迟通过输入电路块提供的启动信号而产生的控制信号，开关MOSFET逐步导通，以便执行每个工作电压的供应。

117. 发明授权

US06339552B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06339552B1
公开(公告)日：2002-01-15
申请号：US09640762
申请日：2000-08-18
申请人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
发明人： Binhaku Taruishi , Hiroki Miyashita , Ken Shibata , Masashi Horiguchi
IPC分类号： G11C700
CPC分类号： G11C7/1084 , G11C7/1066 , G11C7/1078 , G11C7/1093 , G11C7/1096
摘要： In a semiconductor device having a data input buffer capable of inputting write data to each of memory units, the data input buffer is changed from an inactive state to an active state after the reception of instruction for a write operation effected on the memory unit. The data input buffer is a differential input buffer having interface specs based on SSTL, for example, which is brought to an active state by the turning on of a power switch to thereby cause a through current to flow and receives a signal therein while immediately following a small change in small-amplitude signal. Since the input buffer is brought to the active state only when the write operation's instruction for the memory unit is provided, the data input buffer is rendered inactive in advance, before the instruction for the write operation is provided, whereby wasteful power consumption is reduced.
摘要翻译：在具有能够向每个存储单元输入写入数据的数据输入缓冲器的半导体器件中，在接收到对存储器单元进行的写入操作的指令之后，数据输入缓冲器从非活动状态改变为有效状态。数据输入缓冲器是具有例如基于SSTL的接口规格的差分输入缓冲器，其通过接通电源开关而进入活动状态，从而使通过电流流过并在其中立即接收信号小振幅信号的小变化。由于只有在提供了写入操作对存储器单元的指令的情况下，输入缓冲器才进入活动状态，所以在提供写入操作的指令之前，预先使数据输入缓冲器无效，从而减少浪费的功耗。

118. 发明授权

US06335565B1 Semiconductor device 有权
公开(公告)号：US06335565B1
公开(公告)日：2002-01-01
申请号：US09319044
申请日：1999-07-30
申请人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
发明人： Toshio Miyamoto , Asao Nishimura , Koki Noguchi , Satoshi Michishita , Masashi Horiguchi , Masaharu Kubo , Kazuyoshi Shiba
IPC分类号： H01L25065
CPC分类号： H01L23/49816 , H01L23/49572 , H01L25/0657 , H01L25/105 , H01L27/10814 , H01L27/10894 , H01L27/118 , H01L2224/16 , H01L2224/73204 , H01L2224/73253 , H01L2225/1029 , H01L2225/1035 , H01L2225/1058 , H01L2225/107 , H01L2924/00014 , H01L2924/01019 , H01L2924/01021 , H01L2924/01055 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01322 , H01L2924/13091 , H01L2924/15311 , H01L2924/15312 , H01L2924/3011 , H01L2924/3511 , H01L2224/0401
摘要： Described herein is a stacked package according to the present invention, wherein a plurality of tape carriers which seal semiconductor chips, are multilayered in upward and downward directions. In the stacked package, one ends of leads formed over the whole surfaces of each tape carrier are electrically connected to their corresponding connecting terminals of the semiconductor chip. Other ends of the leads are electrically connected to their corresponding through holes defined in the tape carrier. Connecting terminals common to the plurality of semiconductor chips are formed at the same places of the plurality of tape carriers and withdrawn to the same external connecting terminals through a plurality of mutually-penetrated through holes.

119. 发明授权

US06212089B1 Semiconductor memory device and defect remedying method thereof 有权
标题翻译：半导体存储器件及其缺陷补救方法
公开(公告)号：US06212089B1
公开(公告)日：2001-04-03
申请号：US09547917
申请日：2000-04-11
申请人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
发明人： Kazuhiko Kajigaya , Kazuyuki Miyazawa , Manabu Tsunozaki , Kazuyoshi Oshima , Takashi Yamazaki , Yuji Sakai , Jiro Sawada , Yasunori Yamaguchi , Tetsurou Matsumoto , Shinji Udo , Hiroshi Yoshioka , Hirokazu Saito , Mitsuhiro Takano , Makoto Morino , Sinichi Miyatake , Eiji Miyamoto , Yasuhiro Kasama , Akira Endo , Ryoichi Hori , Jun Etoh , Masashi Horiguchi , Shinichi Ikenaga , Atsushi Kumata
IPC分类号： G11C1300
CPC分类号： H01L24/06 , G11C5/025 , G11C5/04 , G11C5/063 , G11C11/406 , G11C29/06 , G11C29/12005 , G11C29/12015 , G11C29/24 , G11C29/34 , G11C29/50 , G11C29/50012 , G11C29/70 , G11C29/80 , G11C29/804 , G11C29/832 , G11C29/844 , G11C2029/2602 , H01L24/05 , H01L24/45 , H01L24/48 , H01L27/0207 , H01L27/105 , H01L27/10897 , H01L27/11898 , H01L2224/04042 , H01L2224/05553 , H01L2224/05556 , H01L2224/05624 , H01L2224/32245 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/4826 , H01L2224/48465 , H01L2224/48624 , H01L2224/73215 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01021 , H01L2924/01023 , H01L2924/01024 , H01L2924/01028 , H01L2924/01037 , H01L2924/01038 , H01L2924/01039 , H01L2924/01041 , H01L2924/01043 , H01L2924/0105 , H01L2924/01051 , H01L2924/01052 , H01L2924/01054 , H01L2924/01055 , H01L2924/01058 , H01L2924/01059 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01083 , H01L2924/01084 , H01L2924/12042 , H01L2924/1305 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/30105 , H01L2924/3011 , H01L2924/3025 , H01L2924/00 , H01L2924/00012
摘要： Herein disclosed is a semiconductor memory device, in which peripheral circuits are arranged in a cross area of a semiconductor chip composed of the longitudinal center portions and the transverse center portions, and in which memory arrays are arranged in the four regions which are divided by the cross area. Thanks to this structure in which the peripheral circuits are arranged at the center portion of the chip, the longest signal transmission paths can be shortened to about one half of the chip size to speed up the DRAM which is intended to have a large storage capacity.
摘要翻译：这里公开了一种半导体存储器件，其中外围电路布置在由纵向中心部分和横向中心部分组成的半导体芯片的交叉区域中，并且其中存储器阵列布置在由交叉区域。由于外围电路布置在芯片的中心部分的这种结构，最长的信号传输路径可以缩短到芯片尺寸的大约一半，以加快DRAM的大容量。

120. 发明授权

US5966336A Semiconductor device having redundancy circuit 有权
标题翻译：具有冗余电路的半导体器件
公开(公告)号：US5966336A
公开(公告)日：1999-10-12
申请号：US144258
申请日：1998-08-31
申请人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
发明人： Masashi Horiguchi , Jun Etoh , Masakazu Aoki , Kiyoo Itoh
IPC分类号： G11C5/00 , G11C7/00 , G11C8/00 , G11C29/00
CPC分类号： G11C29/80 , G11C29/785 , G11C29/808
摘要： A redundancy technique is introduced for a semiconductor memory and, more particularly, a redundancy technique for a memory, for example, a dynamic random access memory (DRAM) having a memory array which is divided into memory mats and a storage capacity of 16 mega bits or more. According to the present redundancy technique, for a semiconductor memory including a memory array which has a plurality of word lines, a plurality of bit lines arranged so that two-level crossings are formed between the word lines and the bit lines, memory cells disposed at desired ones of the two-level crossings, and spare bit lines, there is provided a redundancy circuit having a memory for storing therein a defective address existing in the memory array and comparing an address to be accessed with the stored defective address. Each of the address comparing circuits has stored therein the column address of a defective bit line and a part of the row address indicating the memory mat corresponding to the defective bit line.
摘要翻译：为半导体存储器引入冗余技术，更具体地说，涉及一种用于存储器的冗余技术，例如具有存储器阵列的动态随机存取存储器（DRAM），该存储器阵列被分成存储器阵列，存储容量为16兆比特或者更多。根据本技术的冗余技术，对于包含具有多个字线的存储器阵列的半导体存储器，配置成在字线和位线之间形成2级交叉的多位位线，位于提供了两级交叉中的期望的和备用位线，提供了一种冗余电路，其具有用于在其中存储存在于存储器阵列中的缺陷地址并将要访问的地址与存储的缺陷地址进行比较的存储器。每个地址比较电路在其中存储有缺陷位线的列地址和指示与有缺陷位线对应的存储器堆的行地址的一部分。

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