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111. 发明专利

JP2009252811A Silicon carbide semiconductor device, and method of manufacturing the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2009252811A
公开(公告)日：2009-10-29
申请号：JP2008095693
申请日：2008-04-02
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： WATANABE TOMOKATSU , AYA ATSUSHI , MIURA NARIHISA , SAKAI KEIKO , YOSHIDA SHOHEI , TANIOKA HISAKAZU , NAKAO YUKIYASU , TARUI YOICHIRO , IMAIZUMI MASAYUKI
IPC分类号： H01L21/28 , H01L21/20 , H01L21/265 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/7828 , H01L21/046 , H01L21/0485 , H01L29/1608 , H01L29/66068 , H01L29/7802
摘要： PROBLEM TO BE SOLVED: To make the resistivity of a p base ohmic contact of a silicon carbide semiconductor device lower in order to reduce switching loss and the like of the device in consideration that a method for performing implantation at high temperatures is used since the p base ohmic contact consists of a p++ layer formed by high-concentration ion implantation and a metal electrode, and high-concentration ion implantation performed at the room temperature significantly degrades the crystal of the p++ layer to cause a process failure.
SOLUTION: Disclosed is the method of manufacturing the silicon carbide semiconductor device, wherein in the ion implantation process, the temperature of a silicon carbide wafer is maintained in a range from 175 to 300°C, more preferably in a range from 175 to 200°C. The resistivity of the p base ohmic contact using a p++ region formed by ion implantation at a temperature in a range from 175 to 300°C becomes lower than that in the case that the p++ region is formed by ion implantation at a temperature over 300°C. And, any process failure does not occur.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：为了使碳化硅半导体器件的ap基极欧姆接触的电阻率降低，以便考虑到使用在高温下进行注入的方法来降低器件的开关损耗等，因为 p基欧姆接触由通过高浓度离子注入形成的p ++层和金属电极组成，并且在室温下进行的高浓度离子注入显着降低了p ++层的晶体，导致工艺失败。解决方案：公开了制造碳化硅半导体器件的方法，其中在离子注入工艺中，碳化硅晶片的温度保持在175至300℃的范围内，更优选在175的范围内至200℃。使用在175〜300℃的温度下通过离子注入形成的p ++区域的p基欧姆接触的电阻率比通过在300℃以上的温度下离子注入形成p ++区域的情况下低 C。并且，不会发生任何进程故障。版权所有（C）2010，JPO＆INPIT

112. 发明专利

JP2009152356A Nitride semiconductor device and method of manufacturing the same 审中-公开
标题翻译：氮化物半导体器件及其制造方法
公开(公告)号：JP2009152356A
公开(公告)日：2009-07-09
申请号：JP2007328450
申请日：2007-12-20
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SHIOZAWA KATSUOMI , KANEMOTO KYOZO , OISHI TOSHIYUKI , TARUI YOICHIRO , TOKUDA YASUKI
IPC分类号： H01S5/042 , H01L21/28 , H01S5/323
CPC分类号： H01S5/0425 , B82Y20/00 , H01S5/32341 , H01S5/34333
摘要： PROBLEM TO BE SOLVED: To obtain a nitride semiconductor device that can reduce contact resistance at the interface of a p-type electrode and a nitride semiconductor layer. SOLUTION: The nitride semiconductor device 10 includes: a p-type nitride semiconductor layer 1 and a p-type electrode 3 formed on the p-type nitride semiconductor layer 1. The p-type electrode 3 is formed by successive laminations of a metal layer 3a of a metal having a work function of 5.1 eV or more, a Pd layer 3b of palladium (Pd), and a Ta layer 3c of tantalum (Ta) on the P-type nitride semiconductor layer 1. COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：获得能够降低p型电极和氮化物半导体层的界面处的接触电阻的氮化物半导体器件。解决方案：氮化物半导体器件10包括：p型氮化物半导体层1和形成在p型氮化物半导体层1上的p型电极3.p型电极3通过连续叠层形成功函数为5.1eV或更大的金属的金属层3a，钯（Pd）的Pd层3b和钽（Ta）的Ta层3c在P型氮化物半导体层1上。版权所有（C）2009，JPO＆INPIT

113. 发明专利

JP2009135181A Method of manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：JP2009135181A
公开(公告)日：2009-06-18
申请号：JP2007308541
申请日：2007-11-29
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , SUZUKI YOSUKE , SHIOZAWA KATSUOMI , KANEMOTO KYOZO , OISHI TOSHIYUKI , TOKUDA YASUKI , OMORI TATSUO
IPC分类号： H01S5/323 , H01S5/042 , H01S5/22
CPC分类号： H01S5/34333 , B82Y20/00 , H01L33/325 , H01L33/40 , H01S5/0421 , H01S5/0425 , H01S5/22 , H01S5/2214 , H01S5/3063
摘要： PROBLEM TO BE SOLVED: To provide the method of manufacturing a semiconductor device having a semiconductor structure of nitride gallium system which can stably operate for a long time without inviting a deterioration in device performance.
SOLUTION: An oxide film 9 is formed on the surface of a p-type GaN contact layer 7 by oxidizing the p-type GaN contact layer 7 from the surface by supplying gas containing oxygen such as O
2 , O
3 , NO, N
2 O, NO
2 , and the like after forming an insulating film 8 on a portion except for the surface of a ridge portion. Then, a p-type electrode 10 for contact with the p-type GaN contact layer 7 is formed by evaporation and spattering on the oxide film 9 and the insulating film 8. Then, annealing is performed at 400-700 °C in nitrogen, gas containing nitrogen such as NH
3 , and inert gas such as Ar and He.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造半导体器件的方法，该半导体器件具有能够长期稳定地工作的氮化镓系统的半导体结构，而不会引起器件性能的劣化。解决方案：在p型GaN接触层7的表面上形成氧化物膜9，该氧化物膜9通过供给含有氧气的气体从表面氧化p型GaN接触层7， SB>，O 3 ，NO，N 2 O，NO 2 等在形成绝缘膜8之后脊部的表面。然后，通过在氧化膜9和绝缘膜8上蒸发和溅射形成用于与p型GaN接触层7接触的p型电极10.然后，在氮气中在400-700℃进行退火，含有氮气的气体，例如NH 3 SB，惰性气体如Ar和He。版权所有（C）2009，JPO＆INPIT

114. 发明专利

JP2009094314A Semiconductor device with vertical mosfet structure 有权
标题翻译：具有垂直MOSFET结构的半导体器件
公开(公告)号：JP2009094314A
公开(公告)日：2009-04-30
申请号：JP2007263993
申请日：2007-10-10
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YUYA NAOKI , WATANABE HIROSHI , TARUI YOICHIRO , MIURA NARIHISA
IPC分类号： H01L29/78 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with a vertical MOSFET structure that can reduce ON-resistance and the variation of the ON-resistance.
SOLUTION: This semiconductor device 1 comprises an n-type drift region 2 formed on one main surface of a semiconductor substrate 1, a plurality of p-type base regions 4 formed on the front layer of the drift region 2 with spacing therebetween, n
+ -type source regions 3 formed on each of the front layer of a predetermined number of base regions 4 out of the plurality of base regions 4 in a way that it may be surrounded by the base region 4, p
+ -type base contact regions 5 formed on each of the front layers of the remaining base regions 4 of the plurality of base region 4 in a way that it may be surrounded by the base region 4, and p-type base region connecting sections 5 formed on the front layer of the drift region 2 that connect with each of the base regions 4 so that the base region 4 formed on the base contact region 5 may be connected with one or more base regions 4 formed on the source region 3.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供具有垂直MOSFET结构的半导体器件，其可以降低导通电阻和导通电阻的变化。解决方案：该半导体器件1包括形成在半导体衬底1的一个主表面上的n型漂移区2，形成在漂移区2的前层上的多个p型基区4，其间隔开，形成在多个基极区域4中的预定数量的基极区域4的前表面的每一个上的n + 型基极接触区域5，其可以被基极区域4包围以及形成在与基底区域4中的每一个连接的漂移区域2的前层上的p型基极区域连接部分5，使得形成在基部接触区域5上的基底区域4可以与一个或多个基底区域4形成在源区域3上。版权所有（C）2009，JPO＆INPIT

115. 发明专利

JP2009064955A Manufacturing method for silicon carbide semiconductor device 有权
标题翻译：硅碳化硅半导体器件的制造方法
公开(公告)号：JP2009064955A
公开(公告)日：2009-03-26
申请号：JP2007231396
申请日：2007-09-06
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , SHIKAMA SHOZO , WATANABE TOMOKATSU
IPC分类号： H01L21/336 , H01L21/265 , H01L21/316 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a silicon carbide semiconductor device which contributes to reduction in manufacturing costs and quality improvement by an improvement in the film quality of an oxide film, an improvement in the properties of the interface between a silicon carbide semiconductor substrate and the oxide film, and an improvement in the properties of the interface between oxide films.
SOLUTION: The manufacturing method includes a step of subjecting the silicon carbide semiconductor substrate to heat treatment following ion implantation to the silicon carbide semiconductor substrate, a step of forming the thin first oxide film serving as a gate insulating film 6 on one surface of the silicon carbide semiconductor substrate, using an oxygen-containing gas, and a step of forming the thick second oxide film serving as the gate insulating film 6 on the first oxide film, using an oxygen-containing gas and a silicon-containing gas. These steps are carried out sequentially in a single heat treatment furnace.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了提供一种通过提高氧化膜的膜质量有助于降低制造成本和质量改进的碳化硅半导体器件的制造方法，改善了氧化膜的界面性质碳化硅半导体衬底和氧化物膜，以及氧化物膜之间的界面的性能的改善。解决方案：制造方法包括以下步骤：在碳化硅半导体衬底上进行离子注入之后对碳化硅半导体衬底进行热处理，在一个表面上形成用作栅极绝缘膜6的薄的第一氧化膜的步骤的碳氧化物半导体衬底，并且使用含氧气体和含硅气体在第一氧化物膜上形成用作栅极绝缘膜6的厚的第二氧化膜的步骤。这些步骤在单个热处理炉中依次进行。版权所有（C）2009，JPO＆INPIT

116. 发明专利

JP2008282976A Manufacturing method of film forming device and silicon carbide semiconductor device 有权
标题翻译：薄膜形成装置和碳化硅半导体器件的制造方法
公开(公告)号：JP2008282976A
公开(公告)日：2008-11-20
申请号：JP2007125607
申请日：2007-05-10
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： AYA ATSUSHI , TARUI YOICHIRO
IPC分类号： H01L21/205 , C23C16/42 , H01L21/336 , H01L29/12 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To provide the manufacturing method of a silicon carbide semiconductor device, which is provided with a film forming process for forming a film including silicon carbide epitaxial film or the like with uniform thickness and uniform quality on a silicon carbide substrate, and its manufacturing device.
SOLUTION: Material gas is made to flow while effecting induction heating of a conductive layer under conditions that the silicon carbide substrate is arranged at the opening part of a susceptor so as to expose the film forming surface of the silicon carbide substrate and an infrared ray absorbing particles are arranged so as to be in contact with a surface opposite to the film forming surface while the susceptor with the silicon carbide substrate arranged thereon is introduced into the reaction tube equipped with the conductive layer on the inside surface thereof.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：将要解决的问题：为了提供一种碳化硅半导体器件的制造方法，该方法设置有用于在碳化硅上形成均匀厚度和质量均匀的碳化硅外延膜等的膜的成膜工艺基板及其制造装置。解决方案：在将碳化硅衬底布置在基座的开口部分以暴露碳化硅衬底的成膜表面的条件下，使材料气体在导电层的感应加热的同时流动，并且红外线吸收粒子被布置成与其形成表面相对的表面接触，而其上布置有碳化硅衬底的基座被引入到其内表面上配有导电层的反应管中。版权所有（C）2009，JPO＆INPIT

117. 发明专利

JP2008252143A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008252143A
公开(公告)日：2008-10-16
申请号：JP2008185860
申请日：2008-07-17
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , MATSUNO YOSHINORI , SUGIMOTO HIROSHI , KURODA KENICHI
IPC分类号： H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To obtain a JTE structure which allows its manufacturing process to be simple, and sufficient breakdown voltage properties to be attained.
SOLUTION: This semiconductor device has an anode electrode 3 making Schottky connection with an n-type drift layer 2 formed on an SiC substrate 1, and a p-type JTE region 6 formed on the periphery thereof. The dopant surface concentration of the JTE region is continuously low outward from an edge. The dopant surface concentration of a portion below the edge is 1.8×10
13 -4×10
13 cm
-2 , and is 1×10
13 -2.5×10
13 cm
-2 in a portion of 15 μm below from the edge.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：获得允许其制造工艺简单的JTE结构，并且可以获得足够的击穿电压特性。解决方案：该半导体器件具有与形成在SiC衬底1上的n型漂移层2和形成在其外围的p型JTE区域6进行肖特基连接的阳极电极3。 JTE区域的掺杂剂表面浓度从边缘向外连续低。边缘以下部分的掺杂剂表面浓度为1.8×10 13 / SP> -4×10 13 cm -2 ，为1×10 在距离边缘15μm以下的部分中 13 -2.5×10 13 cm -2 。版权所有（C）2009，JPO＆INPIT

118. 发明专利

JP2008153358A Method of manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：JP2008153358A
公开(公告)日：2008-07-03
申请号：JP2006338416
申请日：2006-12-15
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： TARUI YOICHIRO
IPC分类号： H01L21/329 , H01L21/28 , H01L21/283 , H01L21/336 , H01L29/06 , H01L29/12 , H01L29/47 , H01L29/78 , H01L29/861 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon carbide semiconductor device which can eliminate a fixed charge existing in an insulation film which has an impact on the voltage withstanding performance by a simple method. SOLUTION: The method of manufacturing a silicon carbide semiconductor device includes a process forming a p - type electric field relaxing region 4 by ion implantation in the surface of a silicon carbide wafer consisting of an n - type silicon carbide layer 2 formed on an n + type silicon carbide substrate 1 by an epitaxial crystal growth method; a process of forming an insulation film 7 on the electric field relaxing region 4 by a chemical vapor deposition method; and a process of removing a surface portion of the insulation film 7 by etching to form an insulation film 7'. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：解决的问题：提供一种制造碳化硅半导体器件的方法，其可以通过简单的方法消除存在于对耐电压性能产生影响的绝缘膜中的固定电荷。解决方案：制造碳化硅半导体器件的方法包括通过离子注入在由n - / SP>型电场弛豫区4的工艺通过外延晶体生长法在n + 型碳化硅衬底1上形成的型碳化硅层2; 通过化学气相沉积法在电场缓和区4上形成绝缘膜7的工艺; 以及通过蚀刻去除绝缘膜7的表面部分以形成绝缘膜7'的工艺。版权所有（C）2008，JPO＆INPIT

119. 发明专利

JP2007281157A Manufacturing method for semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：JP2007281157A
公开(公告)日：2007-10-25
申请号：JP2006104910
申请日：2006-04-06
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： YUYA NAOKI , TARUI YOICHIRO , WATANABE HIROSHI
IPC分类号： H01L21/027
摘要： PROBLEM TO BE SOLVED: To provide an alignment mark of a semiconductor device whereby its highly accurate alignment is made even after its high-temperature annealing.
SOLUTION: In a manufacturing method for semiconductor devices, a groove portion comprising step portions 2 is formed in the principal surface of a substrate 1 of a semiconductor device. Then, an alignment mark 10 is formed by so forming a carbon film 3 as to cover the groove portion with it. The shape of the groove is prevented from collapsing after the high-temperature annealing of the semiconductor device, by covering the groove portion with the carbon film 3, because the carbon film 3 is heat-resistant. Since the shape of the groove portion is suppressed from collapsing, the highly accurate mask-alignment of the semiconductor device is made even after its high-temperature annealing.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：提供半导体器件的对准标记，由此即使在其高温退火之后也进行高精度对准。解决方案：在半导体器件的制造方法中，在半导体器件的衬底1的主表面上形成包括台阶部分2的沟槽部分。然后，通过形成碳膜3形成对准标记10，以便覆盖槽部。因为碳膜3是耐热的，所以通过用碳膜3覆盖沟槽部分，防止了半导体器件的高温退火之后槽的形状塌陷。由于凹槽部分的形状被抑制塌陷，所以即使在其高温退火之后也能够进行半导体器件的高度准确的掩模取向。版权所有（C）2008，JPO＆INPIT

120. 发明专利

JP2007103564A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2007103564A
公开(公告)日：2007-04-19
申请号：JP2005289852
申请日：2005-10-03
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , MIURA NARIHISA , FUJIHIRA KEIKO , TARUI YOICHIRO , SUGIMOTO HIROSHI
IPC分类号： H01L29/78 , H01L21/336 , H01L29/12
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of sufficiently securing breakdown voltage between a base region and a drain region of an SiC power device and having a depression region capable of preventing an increase of an electric field in a gate insulation film while keeping withstand voltage between a source and a drain.
SOLUTION: The semiconductor device has impurity surface density within a range of 2.5×10
12 to 7.5×10
12 cm
-2 corresponding to a product of a width 17 of an n-type SiC depression region 10 in an element unit structure extending in the normal line direction from an adjacent surface to a p-type SiC base region 6 and volume concentration of impurities in the depression region 10, and has p-type impurity concentration within a range of 1.5×10
17 to 2.5×10
17 cm
-3 in the p-type SiC base region 6 located below a part (corresponding to a p-type SiC base region 7) between an n-type SiC source region 4 and the depression region 10 and the vicinity (corresponding to a p-type SiC base region 8) of the border with an n-type SiC drift layer 2 in the base region 6.
COPYRIGHT: (C)2007,JPO&INPIT
摘要翻译：要解决的问题：提供能够充分确保SiC功率器件的基极区域和漏极区域之间的击穿电压并具有能够防止栅极绝缘中的电场增加的凹陷区域的半导体器件同时保持源极和漏极之间的耐受电压。解决方案：半导体器件的杂质表面密度在2.5×10 12 至7.5×10 12 cm -2 的范围内涉及在从相邻的表面延伸到p型SiC基区6的法线方向的元件单元结构中的n型SiC凹陷区域10的宽度17的乘积和凹陷区域10中的杂质的体积浓度并且在p型中具有在1.5×10 17 至2.5×10 17 cm -3 的范围内的p型杂质浓度位于n型SiC源极区域4和凹陷区域10之间的部分（对应于p型SiC基极区域7）的下方的SiC基极区域6（与p型SiC基极区域8对应）在基区6中与n型SiC漂移层2的边界。版权所有（C）2007，JPO＆INPIT

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