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1. 发明专利

JP2012248648A Method for manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：JP2012248648A
公开(公告)日：2012-12-13
申请号：JP2011118661
申请日：2011-05-27
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MATSUNO YOSHINORI , TARUI YOICHIRO
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872
CPC分类号： H01L29/1608 , H01L21/0465 , H01L21/0485 , H01L29/0615 , H01L29/0619 , H01L29/6606 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device capable of stabilizing forward characteristics of a diode, specifically a barrier height φB thereof, to reduce variation in leakage current, in manufacturing a silicon carbide Schottky diode.SOLUTION: A method for manufacturing a silicon carbide semiconductor device includes the successive steps of: forming a silicon oxide film OX1 on an epitaxial layer 2 by dry thermal oxidation; forming an ohmic electrode 3 on a back surface of an SiC substrate 1; annealing the SiC substrate 1 to form an ohmic junction between the ohmic electrode 3 and the back surface of the SiC substrate 1; forming a Schottky electrode 4 on the epitaxial layer 2 after removing the silicon oxide film OX1; and performing sintering to form a Schottky junction between the Schottky electrode 4 and the epitaxial layer.
摘要翻译：要解决的问题：在制造碳化硅肖特基二极管时，提供能够稳定二极管的正向特性的半导体器件，特别是其阻挡高度φB，以减小漏电流的变化。解决方案：一种用于制造碳化硅半导体器件的方法包括以下连续步骤：通过干热氧化在外延层2上形成氧化硅膜OX1; 在SiC衬底1的背面上形成欧姆电极3; 退火SiC衬底1以在欧姆电极3和SiC衬底1的背面之间形成欧姆结; 在去除氧化硅膜OX1之后，在外延层2上形成肖特基电极4; 并进行烧结以在肖特基电极4和外延层之间形成肖特基结。版权所有（C）2013，JPO＆INPIT

2. 发明专利

JP2010068008A Method of manufacturing silicon carbide schottky barrier diode 审中-公开
标题翻译：制造碳化硅肖特基二极管的方法
公开(公告)号：JP2010068008A
公开(公告)日：2010-03-25
申请号：JP2009292384
申请日：2009-12-24
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MATSUNO YOSHINORI , OTSUKA KENICHI , KURODA KENICHI , SHIKAMA SHOZO , YUYA NAOKI
IPC分类号： H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing silicon carbide Schottky barrier diodes having uniform characteristics by reducing variations in their forward characteristics. SOLUTION: The silicon carbide Schottky barrier diode is manufactured in the steps of: (a) preparing a silicon carbide substrate; (b) forming an epitaxial layer on one principal surface of the silicon carbide substrate; (c) forming a protective film on the epitaxial layer; (d) forming a first metal layer on another principal surface of the silicon carbide substrate; (e) heat-treating the silicon carbide substrate at a prescribed temperature to form ohmic bonding between the first metal layer and the another principal surface of the silicon carbide substrate; (f) removing the protective film; (g) forming a Ti layer on the epitaxial layer; (h) and heat-treating the silicon carbide substrate at 400-600°C to reduce variations in barrier height of a Schottky junction between the Ti layer and the epitaxial layer. COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：解决的问题：提供通过减少其正向特性的变化来制造具有均匀特性的碳化硅肖特基势垒二极管的方法。解决方案：碳化硅肖特基势垒二极管以下列步骤制造：（a）制备碳化硅衬底; （b）在碳化硅衬底的一个主表面上形成外延层; （c）在外延层上形成保护膜; （d）在碳化硅衬底的另一个主表面上形成第一金属层; （e）在规定温度下对所述碳化硅衬底进行热处理，以在所述第一金属层与所述碳化硅衬底的另一主表面之间形成欧姆接合; （f）去除保护膜; （g）在外延层上形成Ti层; （h）并在400-600℃下热处理碳化硅衬底以减小Ti层和外延层之间的肖特基结的势垒高度的变化。版权所有（C）2010，JPO＆INPIT

3. 发明专利

JP2009059862A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2009059862A
公开(公告)日：2009-03-19
申请号：JP2007225466
申请日：2007-08-31
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , WATANABE TOMOKATSU , SAKAI KEIKO , MATSUNO YOSHINORI
IPC分类号： H01L21/28 , H01L29/861
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor device with resistance so low as to inhibit a raise in device operating voltage, which is obtained by using electrodes containing a non-ohmic constituent whose current/voltage characteristic in contact with a p-type contact region is not linear.
SOLUTION: The semiconductor device has a p-type contact region 4 and a metal electrode 6 formed on the p-type contact region 4. In this case, the relationship of an acceptor concentration N
A (/cm
3 ) on the surface of the p-type contact region 4 and a barrier height ϕ(eV) of the p-type contact region 4 and metal of the metal electrode 6 is set so as to satisfy the formula=0.043LN(N
A )-1.63 A )-1.85.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了获得具有如此低的电阻的半导体器件，以便抑制器件工作电压的升高，这是通过使用包含与p型电极接触的电流/电压特性的非欧姆成分的电极而获得的，类型接触区域不是线性的。解决方案：半导体器件具有p型接触区域4和形成在p型接触区域4上的金属电极6.在这种情况下，受主浓度N A 在p型接触区域4的表面上的（/ cm 3 / SP 3）和p型接触区域4的金属和金属电极6的势垒高度φ（eV）设定为以满足公式= 0.043LN（N A ） - 1.63 <φ<0.052LN（N A ） - 1.85。版权所有（C）2009，JPO＆INPIT

4. 发明专利

JP2004363515A Method of manufacturing silicon carbide semiconductor device 有权
公开(公告)号：JP2004363515A
公开(公告)日：2004-12-24
申请号：JP2003163379
申请日：2003-06-09
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： SUGIMOTO HIROSHI , OTSUKA KENICHI , MATSUNO YOSHINORI , TARUI YOICHIRO
IPC分类号： H01L21/265 , H01L21/336 , H01L29/12 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/1095 , H01L29/66068
摘要： PROBLEM TO BE SOLVED: To manufacture a silicon carbide semiconductor device with a good repeatability and uniformity at a low cost.
SOLUTION: A method of manufacturing silicon carbide semiconductor device contains the steps of epitaxially growing a first conductive type silicon carbide drift layer 2 on a first conductive type silicon carbide substrate 1, forming an ion implantation extended layer 3 on the silicon carbide drift layer 2, forming an ion implantation mask 4 having an opening in a region corresponding to a base region on the ion implantation extended layer 3, ion-implanting a second conductive type impurity in the ion implantation extended layer 3 and the silicon carbide drift layer 2 by using the ion implantation mask 4, removing the ion implantation extended layer 3 of an opening bottom by etching, ion-implanting a first conductive type impurity in the silicon carbide drift layer 2 by using the ion implantation mask 4, removing the ion implantation mask 4 and the ion implantation extended layer 3, and forming a gate electrode 9 between the base regions.
COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2013187438A Silicon carbide semiconductor device and manufacturing method of the same 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：JP2013187438A
公开(公告)日：2013-09-19
申请号：JP2012052546
申请日：2012-03-09
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MATSUNO YOSHINORI
IPC分类号： H01L29/47 , H01L21/28 , H01L21/301 , H01L29/872
CPC分类号： H01L29/1608 , H01L21/045 , H01L21/78 , H01L23/293 , H01L23/3185 , H01L24/03 , H01L24/05 , H01L24/06 , H01L29/6606 , H01L29/872 , H01L2224/02166 , H01L2224/0345 , H01L2224/0381 , H01L2224/0382 , H01L2224/04042 , H01L2224/05155 , H01L2224/05166 , H01L2224/0518 , H01L2224/05184 , H01L2224/05564 , H01L2224/05567 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/06181 , H01L2224/94 , H01L2924/00014 , H01L2924/10272 , H01L2924/12032 , H01L2924/12042 , H01L2924/13052 , H01L2924/1306 , H01L2924/13091 , H01L2224/03 , H01L2924/00 , H01L2224/05552
摘要： PROBLEM TO BE SOLVED: To provide a silicon carbide semiconductor device which is to be divided into a plurality of chips and which can inhibit generation of electric discharge after being divided, and provide a manufacturing method of the silicon carbide semiconductor device.SOLUTION: A silicon carbide semiconductor device of a present embodiment comprises: an n+ type substrate 1; a drift epitaxial layer 2 which is formed on the n+ type substrate 1 and which has an impurity concentration lower than the n+ type substrate 1; a Schottky electrode 6 formed on the drift epitaxial layer 2; and PI (polyimide) 8 which serves as an insulation film and which is formed to cover ends of the Schottky electrode 6 and ends and lateral faces of the drift epitaxial layer 2.
摘要翻译：要解决的问题：提供一种被划分成多个芯片的碳化硅半导体器件，并且能够抑制分割后的放电产生，并提供碳化硅半导体器件的制造方法。解决方案：硅本实施例的碳化物半导体器件包括：n +型衬底1; 漂移外延层2，其形成在n +型衬底1上，其杂质浓度低于n +型衬底1; 形成在漂移外延层2上的肖特基电极6; 和作为绝缘膜的PI（聚酰亚胺）8，其被形成为覆盖肖特基电极6的端部以及漂移外延层2的端面和侧面。

6. 发明专利

JP2008252143A Semiconductor device 审中-公开
标题翻译：半导体器件
公开(公告)号：JP2008252143A
公开(公告)日：2008-10-16
申请号：JP2008185860
申请日：2008-07-17
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , TARUI YOICHIRO , MATSUNO YOSHINORI , SUGIMOTO HIROSHI , KURODA KENICHI
IPC分类号： H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To obtain a JTE structure which allows its manufacturing process to be simple, and sufficient breakdown voltage properties to be attained.
SOLUTION: This semiconductor device has an anode electrode 3 making Schottky connection with an n-type drift layer 2 formed on an SiC substrate 1, and a p-type JTE region 6 formed on the periphery thereof. The dopant surface concentration of the JTE region is continuously low outward from an edge. The dopant surface concentration of a portion below the edge is 1.8×10
13 -4×10
13 cm
-2 , and is 1×10
13 -2.5×10
13 cm
-2 in a portion of 15 μm below from the edge.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：获得允许其制造工艺简单的JTE结构，并且可以获得足够的击穿电压特性。解决方案：该半导体器件具有与形成在SiC衬底1上的n型漂移层2和形成在其外围的p型JTE区域6进行肖特基连接的阳极电极3。 JTE区域的掺杂剂表面浓度从边缘向外连续低。边缘以下部分的掺杂剂表面浓度为1.8×10 13 / SP> -4×10 13 cm -2 ，为1×10 在距离边缘15μm以下的部分中 13 -2.5×10 13 cm -2 。版权所有（C）2009，JPO＆INPIT

7. 发明专利

JP2015005635A 炭化珪素半導体装置の製造方法有权
标题翻译：硅碳化硅半导体器件的制造方法
公开(公告)号：JP2015005635A
公开(公告)日：2015-01-08
申请号：JP2013130257
申请日：2013-06-21
申请人：三菱電機株式会社 , Mitsubishi Electric Corp
发明人： MATSUNO YOSHINORI
IPC分类号： H01L21/28 , H01L21/02 , H01L29/41 , H01L29/47 , H01L29/872
摘要：【課題】本発明は、裏面オーミックを形成する際の基板割れを抑制することができる炭化珪素半導体装置の製造方法を提供することを目的とする。【解決手段】本発明は、(a)炭化珪素半導体基板(1)のおもて面および裏面の少なくとも一方において膜構造(2、3)を形成し、かつ、前記炭化珪素半導体基板(1)の端部を露出させる工程と、(b)前記炭化珪素半導体基板(1)の裏面において熱処理を行い、オーミック接合を形成する工程とを備える。【選択図】図1
摘要翻译：要解决的问题：提供一种碳化硅半导体器件的制造方法，其能够抑制形成背面电阻期间的衬底中的裂纹。解决方案：本发明包括：用于形成膜结构（2， 3）在碳化硅半导体衬底（1）的前表面和后表面中的至少一个中并暴露所述碳化硅半导体衬底（1）的端部; 步骤（b），用于在碳化硅半导体衬底（1）的背面进行热处理并形成欧姆结。

8. 发明专利

JP2014027296A Method for manufacturing silicon carbide schottky barrier diode 有权
标题翻译：制造碳化硅肖特基二极管的方法
公开(公告)号：JP2014027296A
公开(公告)日：2014-02-06
申请号：JP2013207209
申请日：2013-10-02
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： MATSUNO YOSHINORI , OTSUKA KENICHI , KURODA KENICHI , SHIKAMA SHOZO , YUYA NAOKI
IPC分类号： H01L21/329 , H01L29/47 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a method capable of manufacturing a silicon carbide Schottky barrier diode having uniform characteristics by reducing variations in forward characteristics.SOLUTION: A method for manufacturing a silicon carbide Schottky barrier diode comprises steps of: (a) forming an epitaxial layer on one principal surface of a silicon carbide substrate; (b) forming a protective film on the epitaxial layer after the step (a); (c) forming a first metal layer on the other principal surface of the silicon carbide substrate after the step (b); (d) forming an ohmic junction between the first metal layer and the other principal surface of the silicon carbide substrate by thermally processing the silicon carbide substrate at a prescribed temperature after the step (c); (e) removing the whole surface of the protective film from the epitaxial layer after the step (d); (f) forming a Ti layer on the epitaxial layer after the step (e); and (g) thermally processing the silicon carbide substrate at a temperature of not less than 400°C and not more than 600°C after the step (f).
摘要翻译：要解决的问题：提供一种能够通过减少正向特性的变化来制造具有均匀特性的碳化硅肖特基势垒二极管的方法。解决方案：制造碳化硅肖特基势垒二极管的方法包括以下步骤：（a）形成外延层在碳化硅衬底的一个主表面上; （b）在步骤（a）之后在外延层上形成保护膜; （c）在步骤（b）之后在所述碳化硅衬底的另一个主表面上形成第一金属层; （d）通过在步骤（c）之后在规定温度下热处理碳化硅衬底，在第一金属层和碳化硅衬底的另一个主表面之间形成欧姆结; （e）在步骤（d）之后从外延层去除保护膜的整个表面; （f）在步骤（e）之后在外延层上形成Ti层; 和（g）在步骤（f）之后，在不低于400℃且不高于600℃的温度下对碳化硅衬底进行热处理。

9. 发明专利

JP2010140939A Method of manufacturing silicon carbide semiconductor device 有权
标题翻译：制造碳化硅半导体器件的方法
公开(公告)号：JP2010140939A
公开(公告)日：2010-06-24
申请号：JP2008313043
申请日：2008-12-09
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： KURODA KENICHI , WATANABE HIROSHI , MATSUNO YOSHINORI , OTSUKA KENICHI , YUYA NAOKI
IPC分类号： H01L29/47 , H01L29/872
CPC分类号： H01L29/1608 , H01L29/0619 , H01L29/66143 , H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a method of manufacturing a silicon carbide semiconductor device reducing the thickness reducing amount of an ion-implanted layer or an ion-implanted region.
SOLUTION: The method of manufacturing the silicon carbide semiconductor device includes the steps of (a) selectively implanting ions onto a silicon carbide layer 2 formed on a silicon carbide substrate 1 to subject the silicon carbide layer 2 to activation annealing, (b) masking the ion-implanted layer 3 being the ion-implanted region with a photo-resist 5, (c) dry-etching a surface layer of the silicon carbide layer 2 using the photo-resist 5 as a mask, (d) removing the photo-resist 5, (e) after the step (d), forming a sacrificial oxide film 7 on the entire surface layer of the silicon carbide layer 2, and (f) removing the sacrificial oxide film 7 by wet-etching.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种制造减小离子注入层或离子注入区域的厚度减少量的碳化硅半导体器件的方法。解决方案：制造碳化硅半导体器件的方法包括以下步骤：（a）将选择性地将离子注入到形成在碳化硅衬底1上的碳化硅层2上以使碳化硅层2活化退火，（b ）用光致抗蚀剂5掩蔽作为离子注入区的离子注入层3，（c）使用光致抗蚀剂5作为掩模对碳化硅层2的表面层进行干蚀刻，（d）去除光刻胶5（e）在步骤（d）之后，在碳化硅层2的整个表面层上形成牺牲氧化膜7，（f）通过湿法蚀刻除去牺牲氧化膜7。版权所有（C）2010，JPO＆INPIT

10. 发明专利

JP2010087483A Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：JP2010087483A
公开(公告)日：2010-04-15
申请号：JP2009195323
申请日：2009-08-26
申请人： Mitsubishi Electric Corp , 三菱電機株式会社
发明人： OTSUKA KENICHI , MATSUNO YOSHINORI , KURODA KENICHI , SHIKAMA SHOZO
IPC分类号： H01L29/47 , H01L29/861 , H01L29/872
CPC分类号： H01L29/872
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor device with low operating voltage over a wide current density range.
SOLUTION: The semiconductor device 10 includes: a first conductivity-type semiconductor substrate 1; a first conductivity-type semiconductor layer 2 that is formed on the semiconductor substrate 1 with a lower doping concentration than that of the semiconductor substrate 1; first second-conductivity-type semiconductor regions 3 that are formed side by side at a predetermined interval on the outer surface of the semiconductor layer 2; a first electrode 5 that is formed on the semiconductor layer 2 and the first semiconductor regions 3 to form a Schottky contact with the semiconductor layer 2 and form an Ohmic-contact with the first semiconductor regions 3; and a second electrode 6 that is formed on the backside of the semiconductor substrate 1, wherein the width Wp (μm) of the first semiconductor region 3 and doping concentration N (cm
-3 ) of the semiconductor layer 2 have a relationship of Wp>-72×In(N)+2,685.
COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：在宽电流密度范围内提供具有低工作电压的半导体器件。解决方案：半导体器件10包括：第一导电型半导体衬底1; 在半导体衬底1上形成的掺杂浓度低于半导体衬底1的掺杂浓度的第一导电型半导体层2; 在半导体层2的外表面上以预定间隔并排形成的第一第二导电型半导体区域3; 形成在半导体层2和第一半导体区域3上以与半导体层2形成肖特基接触并与第一半导体区域3形成欧姆接触的第一电极5; 以及形成在半导体衬底1的背面上的第二电极6，其中第一半导体区域3的宽度Wp（μm）和半导体层的掺杂浓度N（cm -3 ） 2具有Wp> -72×In（N）+2,685的关系。版权所有（C）2010，JPO＆INPIT

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