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111. 发明授权

US5343089A Sample-and-hold circuit device 失效
标题翻译：采样保持电路装置
公开(公告)号：US5343089A
公开(公告)日：1994-08-30
申请号：US155905
申请日：1993-11-23
申请人： Tetsuro Itakura , Takeshi Shima
发明人： Tetsuro Itakura , Takeshi Shima
IPC分类号： G09G3/36 , G11C27/02
CPC分类号： G11C27/026 , G11C27/024 , G09G2310/0289 , G09G3/3688
摘要： A sample-and-hold circuit includes a first switch element which is opened or closed in accordance with a first control signal so as to selectively connect an input signal terminal for receiving an input signal to an internal terminal, a non-linear element for connecting the internal terminal to an output terminal, a potential holding circuit connected between the output terminal and ground, and a second switch element or a current source circuit which is controlled by a second control signal so as to selectively connect the output terminal to ground.
摘要翻译：采样保持电路包括根据第一控制信号打开或关闭的第一开关元件，以选择性地将用于接收输入信号的输入信号端子连接到内部端子，用于连接的非线性元件输出端子的内部端子，连接在输出端子和地之间的电位保持电路以及由第二控制信号控制的第二开关元件或电流源电路，以选择性地将输出端子连接到地。

112. 发明授权

US09225168B2 Switching power supply device and control circuit thereof 有权
标题翻译：开关电源装置及其控制电路
公开(公告)号：US09225168B2
公开(公告)日：2015-12-29
申请号：US13692044
申请日：2012-12-03
申请人： Taichi Ogawa , Takeshi Ueno , Tetsuro Itakura
发明人： Taichi Ogawa , Takeshi Ueno , Tetsuro Itakura
IPC分类号： H02J1/00 , H02M3/158 , H02M3/156
CPC分类号： H02J1/00 , H02M3/158 , H02M2003/1566 , Y10T307/549
摘要： A control circuit of a switching power supply device has a first current source capable of supplying an auxiliary current to a load resistance of the switching power supply device when a load current flowing through the load resistance increases, a second current source capable of pulling in a current from the load resistance when the load current flowing through the load resistance decreases, and an auxiliary current controller configured to activate the first current source or the second current source from when a variation in the load current flowing through the load resistance is detected to have exceeded a predetermined level until a current flowing through the inductor becomes equal to the current flowing through the load resistance.
摘要翻译：开关电源装置的控制电路具有第一电流源，当流过负载电阻的负载电流增加时能够向开关电源装置的负载电阻提供辅助电流，第二电流源能够拉入当负载电流流过负载电阻的负载电流下降时，负载电阻的电流以及从流过负载电阻的负载电流的变化检测到的第一电流源或第二电流源的辅助电流控制器被配置为具有超过预定电平，直到流过电感器的电流变得等于流过负载电阻的电流。

113. 发明授权

US08604766B2 DC-DC converter and control circuit thereof 失效
标题翻译： DC-DC转换器及其控制电路
公开(公告)号：US08604766B2
公开(公告)日：2013-12-10
申请号：US13692010
申请日：2012-12-03
申请人： Kei Shiraishi , Takeshi Ueno , Taichi Ogawa , Tetsuro Itakura
发明人： Kei Shiraishi , Takeshi Ueno , Taichi Ogawa , Tetsuro Itakura
IPC分类号： G05F1/59
CPC分类号： G05F1/468 , H02M3/157 , H02M2003/1566
摘要： A control circuit of a DC-DC converter has a voltage difference signal generator configured to generate a digital voltage difference signal depending on a voltage difference between the output voltage and a reference voltage, a PID controller configured to generate a digital PID signal for determining the duty ratio of the pulse-width modulated signal, based on the digital voltage difference signal, a phase controller configured to generate a digital phase control signal for determining a phase of the pulse-width modulated signal, based on the digital voltage difference signal, and a PWM generator configured to generate the pulse-width modulated signal, based on the digital PID signal and the digital phase control signal.
摘要翻译： DC-DC转换器的控制电路具有：电压差信号发生器，被配置为根据输出电压和参考电压之间的电压差产生数字电压差信号; PID控制器，被配置为产生数字PID信号以确定基于数字电压差信号的脉宽调制信号的占空比;相位控制器，被配置为基于数字电压差信号产生用于确定脉宽调制信号的相位的数字相位控制信号;以及 PWM发生器，被配置为基于数字PID信号和数字相位控制信号来产生脉宽调制信号。

114. 发明授权

US08537039B2 Distortion correcting device 失效
标题翻译：失真校正装置
公开(公告)号：US08537039B2
公开(公告)日：2013-09-17
申请号：US13409516
申请日：2012-03-01
申请人： Junya Matsuno , Tetsuro Itakura
发明人： Junya Matsuno , Tetsuro Itakura
IPC分类号： H03M1/06
CPC分类号： H03M1/0614 , H03M1/12 , H03M1/1225
摘要： There is provided a distortion correcting device in which a first A/D converter A/D converts a first input signal to obtain a first converted signal, a second A/D converter A/D converts a second input signal to obtain a second converted signal wherein the second input signal is a signal obtained by reducing an amplitude of the first input signal, or the first input signal is a signal obtained by increasing an amplitude of the second input signal, the exponentiator obtains an exponential signal by raising the second converted signal to an n-th power (“n” is an integer of 2 or more), a adaptive correlation controller carries out adaptive correlation control based on the exponential signal and the second converted signal to generate a distortion signal that is an n-th power component contained in the exponential signal, and a distortion remover removes the distortion signal from the first converted signal.
摘要翻译：提供了一种失真校正装置，其中第一A / D转换器A / D转换第一输入信号以获得第一转换信号，第二A / D转换器A / D转换第二输入信号以获得第二转换信号其中所述第二输入信号是通过减小所述第一输入信号的幅度获得的信号，或者所述第一输入信号是通过增加所述第二输入信号的幅度而获得的信号，所述指数器通过提高所述第二转换信号来获得指数信号到“n”次幂（“n”是2以上的整数）时，自适应相关控制器根据指数信号和第二转换信号进行自适应相关控制，生成作为第n次方的失真信号分量包含在指数信号中，并且失真去除器从第一转换信号中去除失真信号。

115. 发明申请

US20120176263A1 CURRENT SWITCH CIRCUIT AND DA CONVERTER 审中-公开
标题翻译：电流开关电路和DA转换器
公开(公告)号：US20120176263A1
公开(公告)日：2012-07-12
申请号：US13237260
申请日：2011-09-20
申请人： Shigeo Imai , Ippei Akita , Tetsuro Itakura
发明人： Shigeo Imai , Ippei Akita , Tetsuro Itakura
IPC分类号： H03M1/66 , H03K17/16
CPC分类号： H03K19/00384 , H03M1/0641 , H03M1/745
摘要： According to one embodiment, a first switch transistor and a second switch transistor convert an input current to a first current and a second current by performing a switching operation on the basis of differential input voltages, respectively. An input current source supplies the input current to the first and second switch transistors. A noise current generating circuit generates a dummy current to simulate a noise current flowing through the input current source. A third switch transistor and a fourth switch transistor convert the dummy current to a third current and a fourth current by performing a switching operation on the basis of differential input voltages and negatively superimposes the third current and the fourth current on the first and second currents, respectively.
摘要翻译：根据一个实施例，第一开关晶体管和第二开关晶体管分别通过基于差分输入电压执行开关操作将输入电流转换为第一电流和第二电流。输入电流源将输入电流提供给第一和第二开关晶体管。噪声电流产生电路产生虚拟电流以模拟流过输入电流源的噪声电流。第三开关晶体管和第四开关晶体管通过基于差分输入电压执行开关操作将虚拟电流转换为第三电流和第四电流，并将第三电流和第四电流负向叠加在第一和第二电流上，分别。

116. 发明授权

US07911281B2 PLL circuit and radio communication apparatus 有权
标题翻译： PLL电路和无线电通信装置
公开(公告)号：US07911281B2
公开(公告)日：2011-03-22
申请号：US12558771
申请日：2009-09-14
申请人： Hiroaki Hoshino , Osamu Watanabe , Shoji Otaka , Tetsuro Itakura
发明人： Hiroaki Hoshino , Osamu Watanabe , Shoji Otaka , Tetsuro Itakura
IPC分类号： H03B5/12 , H03B27/00 , H03L7/18
CPC分类号： H03L7/099 , H03L7/0891 , H03L7/18
摘要： A PLL circuit includes: a voltage-controlled oscillator including: a first oscillating portion configured to generate first differential signals; and a second oscillating portion configured to generate second differential signals with a phase difference of 90 degrees from the first differential signals; a phase detector configured to compare phases of third differential signals based on the first and second differential signals with a phase of a reference signal; and a loop filter configured to generate a control voltage for controlling the voltage-controlled oscillator based on a result of the comparison in the phase detector.
摘要翻译： PLL电路包括：压控振荡器，包括：第一振荡部分，被配置为产生第一差分信号; 以及第二振荡部分，被配置为产生与所述第一差分信号相差90度的第二差分信号; 相位检测器，被配置为将基于第一和第二差分信号的第三差分信号的相位与参考信号的相位进行比较; 以及环路滤波器，其被配置为基于相位检测器中的比较结果产生用于控制压控振荡器的控制电压。

117. 发明申请

US20100149009A1 CALIBRATION METHOD, A/D CONVERTER, AND RADIO DEVICE 有权
标题翻译：校准方法，A / D转换器和无线电设备
公开(公告)号：US20100149009A1
公开(公告)日：2010-06-17
申请号：US12637211
申请日：2009-12-14
申请人： Tomohiko ITO , Tetsuro Itakura
发明人： Tomohiko ITO , Tetsuro Itakura
IPC分类号： H03M1/10
CPC分类号： H03M1/1023 , H03M1/0682 , H03M1/205 , H03M1/365 , H03M1/745
摘要： There is disclosed a calibration method for an A/D converter. The A/D converter includes a first amplifier to amplify first and second voltage signals, a second amplifier to amplify the first and second voltage signals amplified by the first amplifier, and a comparator to compare the first and second voltage signals amplified by the second amplifier. The calibration method performs short-circuiting input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a first result, calibrating output voltage of the second amplifier according to the first result, short-circuiting input ports of the first amplifier, opening the short-circuited input ports of the second amplifier, comparing the first and second voltage signals inputted to the comparator to obtain a second result, and calibrating output voltage of the first amplifier according to the second result.
摘要翻译：公开了一种用于A / D转换器的校准方法。 A / D转换器包括：放大第一和第二电压信号的第一放大器;放大由第一放大器放大的第一和第二电压信号的第二放大器;以及比较器，用于比较由第二放大器放大的第一和第二电压信号; 。校准方法执行第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第一结果，根据第一结果校准第二放大器的输出电压，短路输入端口第一放大器，打开第二放大器的短路输入端口，比较输入到比较器的第一和第二电压信号以获得第二结果，并根据第二结果校准第一放大器的输出电压。

118. 发明授权

US07583948B2 Time constant automatic adjusting circuit, filter circuit system, and method of automatically adjusting time constant 失效
标题翻译：时间常数自动调节电路，滤波电路系统及自动调整时间常数的方法
公开(公告)号：US07583948B2
公开(公告)日：2009-09-01
申请号：US11411939
申请日：2006-04-27
申请人： Osamu Watanabe , Rui Ito , Shigehito Saigusa , Tetsuro Itakura
发明人： Osamu Watanabe , Rui Ito , Shigehito Saigusa , Tetsuro Itakura
IPC分类号： H04B1/00
CPC分类号： H03H11/1291
摘要： A time constant automatic adjusting circuit comprises: a filter circuit varying a phase of an clock signal to be input so as to output the clock signal; a phase comparison circuit comparing a phase of an output signal of the filter circuit with the phase of the clock signal, and outputting a predetermined voltage when the phase of the output signal and the phase of the clock signal are the same; at least three comparators comparing the output voltage with a plurality of different voltages; an up-down counter counting a number of output bits of either one of the at least three different voltages in accordance with an output result of the comparators; and a control circuit varying the time constant of the filter circuit in accordance with the number of output bits counted by the up-down counter.
摘要翻译：时间常数自动调整电路包括：滤波器电路，改变输入时钟信号的相位以输出时钟信号; 相位比较电路，将滤波器电路的输出信号的相位与时钟信号的相位进行比较，并且当输出信号的相位和时钟信号的相位相同时输出预定电压; 至少三个比较器将输出电压与多个不同电压进行比较; 根据比较器的输出结果，计数至少三个不同电压中的任何一个的输出位的数量的递减计数器; 以及控制电路根据由升降计数器计数的输出位数来改变滤波电路的时间常数。

119. 发明申请

US20080284634A1 DIFFERENTIAL AMPLIFYING CIRCUIT 失效
标题翻译：差分放大电路
公开(公告)号：US20080284634A1
公开(公告)日：2008-11-20
申请号：US12173431
申请日：2008-07-15
申请人： Tomohiko Ito , Tetsuro Itakura
发明人： Tomohiko Ito , Tetsuro Itakura
IPC分类号： H03M1/60
CPC分类号： H03F3/45179
摘要： Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same) and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
摘要翻译：公开了一种包括放大电路的差分放大电路，其中1）第六晶体管的漏极连接到第八晶体管的漏极，第十晶体管的漏极连接到第四晶体管的漏极，以及2）第四（或第八）和第十（或第六）晶体管（每单位栅极长度转换，并且随后的栅极宽度相同）的栅极宽度的总和与第五（或第九）晶体管与第一（或第三）和第二（或第四）电流源电路之间的电流比几乎成比例，第四（或第八）晶体管的栅极宽度等于或大于第十（或第六）晶体管的栅极宽度。

120. 发明申请

US20080143434A1 TRANSCONDUCTOR 失效
公开(公告)号：US20080143434A1
公开(公告)日：2008-06-19
申请号：US11847503
申请日：2007-08-30
申请人： Rui Ito , Tetsuro Itakura
发明人： Rui Ito , Tetsuro Itakura
IPC分类号： G06G7/12
CPC分类号： H03G1/0029 , H03F1/3211 , H03F3/45179 , H03F3/45475 , H03F2203/45318 , H03F2203/45342 , H03F2203/45352 , H03F2203/45398 , H03H11/04
摘要： Disclosed is a transconductor including: first and second transistors each having first and second gates, the first and second gates being independently controlled, differential voltage input being supplied between the one first gate and the other first gate, the one source and the other source being connected, a first control voltage being commonly given to both of the second gates, and the drains being differential current output terminals; third and fourth transistors each having the same connection as the first and second transistors, each of the one drain and the other drain being connected with either of the one drain and the other drain of the first and the second transistors so that polarities are opposite to each other; and a current source connected with both of the sources of the first and the second transistors and both of the sources of the third and the fourth transistors.
摘要翻译：公开了一种跨导体，包括：第一和第二晶体管，每个具有第一和第二栅极，第一和第二栅极被独立地控制，差分电压输入被提供在一个第一栅极和另一个第一栅极之间，一个源极和另一个源极所述第一控制电压通常被提供给所述第二栅极，并且所述漏极是差动电流输出端子; 第三和第四晶体管各自具有与第一和第二晶体管相同的连接，一个漏极和另一个漏极中的每一个与第一和第二晶体管的一个漏极和另一个漏极中的任一个连接，使得极性与彼此; 以及与第一和第二晶体管的源极以及第三和第四晶体管的源极两者连接的电流源。

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