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    • 111. 发明申请
      US20070188650A1 IMAGE-CAPTURING APPARATUS 有权
    • IMAGE-CAPTURING APPARATUS
    • 图像捕获设备
    • US20070188650A1
    • 2007-08-16
    • US11563256
    • 2006-11-27
    • Masao Kobayashi , Hideo Nakamura
    • Masao Kobayashi , Hideo Nakamura
    • H04N5/225 , H04N5/232 , G03B13/00 , H04N9/09 , H04N9/097 , G03B41/00
    • H04N5/2259 , G03B19/023 , H04N5/2258 , H04N5/23296 , H04N5/2628 , H04N5/3415
    • A digital camera enables high-speed zooming operation without use of a zoom lens. Light originating from a fixed-focal-length lens is split into two beams by a beam splitter, to thus form respective images on a first image sensor and a second image sensor. The first image sensor and the second image sensor are equal to each other in terms of the number of pixels, but differ from each other in terms of a pixel size. The first image sensor acquires a wide image, and the second image sensor acquires a telephotography image. An output is produced by means of switching between the first image sensor and the second image sensor, in response to zooming operation. When the image from the first image sensor is recorded, focus detection is performed by use of an image signal from the second image sensor, to thus effect automatic focusing.
    • 数码相机可以在不使用变焦镜头的情况下进行高速变焦操作。 源自固定焦距透镜的光被分束器分成两束，从而在第一图像传感器和第二图像传感器上形成相应的图像。 第一图像传感器和第二图像传感器在像素数量方面彼此相等，但是在像素尺寸方面彼此不同。 第一图像传感器获取宽的图像，并且第二图像传感器获取远摄图像。 响应于变焦操作，通过在第一图像传感器和第二图像传感器之间切换产生输出。 当记录来自第一图像传感器的图像时，通过使用来自第二图像传感器的图像信号执行焦点检测，从而实现自动聚焦。
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
    • 118. 发明授权
      US5088023A Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device 失效
    • Integrated circuit having processor coupled by common bus to programmable read only memory for processor operation and processor uncoupled from common bus when programming read only memory from external device
    • US5088023A
    • 1992-02-11
    • US358523
    • 1989-05-30
    • Hideo Nakamura , Terumi Sawase
    • Hideo Nakamura , Terumi Sawase
    • G06F12/00 , G06F12/06 , G06F13/16 , G06F15/17 , G06F15/78
    • G06F15/7842 , G06F15/786
    • The present invention discloses an integrated circuit having a data bus, an address bus, a processor and a memory each connected to the data bus and the address bus, a first transmitter for transmitting data inputted to a data terminal to the data bus, a second transmitter for transmitting data on the data bus to the data terminal, a third transmitter for transmitting an address inputted to an address terminal to the address bus, and signal generate means for generating signals to set the respective outputs from the first and third transmitters to the high impedance in response to a memory read request supplied from the processor, for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory to the data bus, the first transmitter, and the third transmitter to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to output data and an address from the processor to the data bus and the address bus, respectively to the high impedance in response to a memory read request from an external device, and for generating signals to set the respective outputs from the data output of processor module and the address output of processor module in response to a memory write request from an external device, the integrated circuit further including a fourth transmitter for transmitting an address on the address bus to the address terminal, wherein the signal generate means generates signals to set the outputs from the first and third transmitters to the high impedance in response to an external memory read request supplied from the processor, sets the respective outputs from the data output of memory module, the first transmitter, and the third transmitter to the high impedance in response to an external memory write request supplied from the processor, and responds to the read or write request from the external device in preference to the read or write request from the processor.
    • 基本信息 添加关注 加入工作空间 PDF全文 PDF下载 全文下载 相似专利 双屏查看 权利要求书 说明书全文 Global Dossier Espacenet 法律信息 同族专利 专利引用
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