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    • 111. 发明申请
    • FREQUENCY CONVERTING CIRCUIT AND RECEIVER
    • 频率转换电路和接收器
    • US20100112971A1
    • 2010-05-06
    • US12503199
    • 2009-07-15
    • Junya MatsunoTakafumi YamajiTetsuro Itakura
    • Junya MatsunoTakafumi YamajiTetsuro Itakura
    • H04B1/16H04B15/00
    • H04B1/30
    • A receiver includes a multiphase mixer that multiplies a received radio signal by multiphase local signals the number of which is the same as an integer having a first prime factor and a second prime factor different from the first prime factor, and generates first multiphase baseband signals the number of which is the same as the integer, a first processing circuit that suppresses common modes for first multiphase signal groups formed by dividing the first multiphase baseband signals into groups of signals the number of which is the same as the first prime factor, and generates second multiphase baseband signals, and a second processing circuit that suppresses common modes for second multiphase signal groups formed by dividing the second multiphase baseband signals into groups of signals the number of which is the same as the second prime factor, and generates third multiphase baseband signals.
    • 接收机包括:多相混合器,其通过多个本地信号乘以接收的无线电信号,多相本地信号的数量与具有不同于第一素因子的第一素因子和第二素因子的整数相同,并且生成第一多相基带信号 其数量与整数相同,第一处理电路抑制通过将第一多相基带信号划分成与第一素数相同数量的信号组而形成的第一多相信号组的共模,并产生 第二多相基带信号,以及第二处理电路,其抑制通过将第二多相基带信号划分成与第二素因数相同的信号组而形成的第二多相信号组的共模,并且产生第三多相基带信号 。
    • 113. 发明申请
    • DIFFERENTIAL AMPLIFYING CIRCUIT
    • 差分放大电路
    • US20080284634A1
    • 2008-11-20
    • US12173431
    • 2008-07-15
    • Tomohiko ItoTetsuro Itakura
    • Tomohiko ItoTetsuro Itakura
    • H03M1/60
    • H03F3/45179
    • Disclosed is a differential amplifying circuit including an amplifying circuit, wherein 1) a drain of a sixth transistor is connected to a drain of an eighth transistor, and a drain of a tenth transistor is connected to a drain of a fourth transistor, and 2) a ratio between a total of gate widths of the fourth (or eighth) and tenth (or sixth) transistors (converted per unit gate length, and gate widths that follow are the same) and a gate width of a fifth (or ninth) transistor is nearly proportional to a current ratio between a first (or third) and second (or fourth) current source circuits, the gate width of the fourth (or eighth) transistor being equal to or more than that of the tenth (or sixth) transistor.
    • 公开了一种包括放大电路的差分放大电路,其中1)第六晶体管的漏极连接到第八晶体管的漏极,第十晶体管的漏极连接到第四晶体管的漏极,以及2) 第四(或第八)和第十(或第六)晶体管(每单位栅极长度转换,并且随后的栅极宽度相同)的栅极宽度的总和与第五(或第九)晶体管 与第一(或第三)和第二(或第四)电流源电路之间的电流比几乎成比例,第四(或第八)晶体管的栅极宽度等于或大于第十(或第六)晶体管的栅极宽度 。
    • 115. 发明申请
    • TRANSCONDUCTOR
    • US20080143434A1
    • 2008-06-19
    • US11847503
    • 2007-08-30
    • Rui ItoTetsuro Itakura
    • Rui ItoTetsuro Itakura
    • G06G7/12
    • H03G1/0029H03F1/3211H03F3/45179H03F3/45475H03F2203/45318H03F2203/45342H03F2203/45352H03F2203/45398H03H11/04
    • Disclosed is a transconductor including: first and second transistors each having first and second gates, the first and second gates being independently controlled, differential voltage input being supplied between the one first gate and the other first gate, the one source and the other source being connected, a first control voltage being commonly given to both of the second gates, and the drains being differential current output terminals; third and fourth transistors each having the same connection as the first and second transistors, each of the one drain and the other drain being connected with either of the one drain and the other drain of the first and the second transistors so that polarities are opposite to each other; and a current source connected with both of the sources of the first and the second transistors and both of the sources of the third and the fourth transistors.
    • 公开了一种跨导体,包括:第一和第二晶体管,每个具有第一和第二栅极,第一和第二栅极被独立地控制,差分电压输入被提供在一个第一栅极和另一个第一栅极之间,一个源极和另一个源极 所述第一控制电压通常被提供给所述第二栅极,并且所述漏极是差动电流输出端子; 第三和第四晶体管各自具有与第一和第二晶体管相同的连接,一个漏极和另一个漏极中的每一个与第一和第二晶体管的一个漏极和另一个漏极中的任一个连接,使得极性与 彼此; 以及与第一和第二晶体管的源极以及第三和第四晶体管的源极两者连接的电流源。