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111. 发明申请

US20080237796A1 Increasing the surface area of a memory cell capacitor 有权
标题翻译：增加存储单元电容器的表面积
公开(公告)号：US20080237796A1
公开(公告)日：2008-10-02
申请号：US11731193
申请日：2007-03-30
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。在第三绝缘层上沉积第二导电层。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

112. 发明申请

US20070168848A1 Error-detection flip-flop 有权
标题翻译：错误检测触发器
公开(公告)号：US20070168848A1
公开(公告)日：2007-07-19
申请号：US11323675
申请日：2005-12-30
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： G06F11/00
CPC分类号： G01R31/31937 , G01R31/31726
摘要： An error-detection flip-flop is disclosed for identifying timing errors in digital circuits. The error-detection flip-flop is a master-slave flip-flop including logic to determine whether an input signal is received during a predetermined clock period, signifying a timing error. The error-detection flip-flop produces a variable-length error pulse, which may be combined with other error pulses and converted to a stable signal for sampling by error-correction circuitry. The error-detection flip-flop does not increase the clocking power of the digital circuit and consumes little additional circuit area.
摘要翻译：公开了用于识别数字电路中的定时误差的错误检测触发器。误差检测触发器是主从触发器，其包括用于确定在预定时钟周期期间是否接收到输入信号的逻辑，表示定时误差。误差检测触发器产生可变长度误差脉冲，其可以与其他误差脉冲组合并转换成用于由纠错电路进行采样的稳定信号。误差检测触发器不会增加数字电路的时钟功率，并且消耗少量额外的电路面积。

113. 发明申请

US20070164371A1 Reliability degradation compensation using body bias 审中-公开
标题翻译：使用身体偏倚的可靠性退化补偿
公开(公告)号：US20070164371A1
公开(公告)日：2007-07-19
申请号：US11321100
申请日：2005-12-29
申请人： James Tschanz , Subhasish Mitra , Vivek De
发明人： James Tschanz , Subhasish Mitra , Vivek De
IPC分类号： H01L29/76
CPC分类号： G01R31/2642
摘要： A system may include detection of reliability degradation of a transistor, and change of a body bias applied to the transistor based on the detected reliability degradation.
摘要翻译：系统可以包括基于检测到的可靠性降级来检测晶体管的可靠性劣化以及施加到晶体管的体偏置的变化。

114. 发明申请

US20070024322A1 Leakage current reduction scheme for domino circuits 审中-公开
标题翻译：多米诺骨电路泄漏电流削减方案
公开(公告)号：US20070024322A1
公开(公告)日：2007-02-01
申请号：US11194946
申请日：2005-08-01
申请人： Yibin Ye , Siva Narendra , Vivek De
发明人： Yibin Ye , Siva Narendra , Vivek De
IPC分类号： H03K19/096
CPC分类号： H03K19/0016
摘要： A method and system for leakage current reduction in domino circuits is described. The system includes a domino circuit with a dynamic gate, a static gate, and a standby signal to set the domino circuit to an evaluate phase during an inactive mode. The inputs to the static gate are set to low and the inputs to the dynamic gate are set to high during the inactive mode. The standby signal may be an input to a device in the dynamic gate or an input to a latch coupled to the dynamic gate.
摘要翻译：描述了多米诺骨电路中泄漏电流降低的方法和系统。该系统包括具有动态门，静态门和备用信号的多米诺骨牌电路，以在非活动模式期间将多米诺骨牌电路设置为评估阶段。静态门的输入被设置为低电平，并且在非活动模式期间将动态门的输入设置为高电平。备用信号可以是对动态门中的设备的输入或耦合到动态门的锁存器的输入。

115. 发明申请

US20060268626A1 Memory with dynamically adjustable supply 有权
标题翻译：内存动态可调电源
公开(公告)号：US20060268626A1
公开(公告)日：2006-11-30
申请号：US11137905
申请日：2005-05-25
申请人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
发明人： Fatih Hamzaoglu , Kevin Zhang , Nam Kim , Muhammad Khellah , Dinesh Somasekhar , Yibin Ye , Vivek De , Bo Zheng
IPC分类号： G11C7/10
CPC分类号： G11C5/14 , G11C11/413
摘要： In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.
摘要翻译：在一些实施例中，存储器阵列具有当写入或读取时可以具有修改的电源以增强其读取稳定性和/或写入裕度性能的单元。可以公开和/或要求保护其他实施例。

116. 发明申请

US20060259890A1 Method and apparatus for power consumption reduction 失效
标题翻译：降低功耗的方法和装置
公开(公告)号：US20060259890A1
公开(公告)日：2006-11-16
申请号：US11486030
申请日：2006-07-14
申请人： James Tschanz , Nasser Kurd , Javed Barkatullah , Vivek De
发明人： James Tschanz , Nasser Kurd , Javed Barkatullah , Vivek De
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and chip design are provided for reducing power consumption. A first functional block having a phase logic circuit may be provided in a first area of a chip. A second functional block having an edge-triggered circuit may be provided in a second area of the chip. Edge-triggered circuits within the second functional block may be replaced with dual edge-triggered circuits. Phase logic circuits may be clocked by a full frequency clock signal and dual edge-triggered circuits may be clocked by a half-frequency clock signal.
摘要翻译：提供了一种降低功耗的方法和芯片设计。具有相位逻辑电路的第一功能块可以设置在芯片的第一区域中。具有边缘触发电路的第二功能块可以设置在芯片的第二区域中。第二功能块内的边沿触发电路可以用双边沿触发电路代替。相位逻辑电路可以由全频时钟信号来计时，并且双边沿触发电路可以由半频时钟信号来计时。

117. 发明申请

US20060226863A1 Method and apparatus to adjust die frequency 审中-公开
标题翻译：调整芯片频率的方法和装置
公开(公告)号：US20060226863A1
公开(公告)日：2006-10-12
申请号：US11094574
申请日：2005-03-31
申请人： Siva Narendra , James Tschanz , Victor Zia , Badarinath Kommandur , Tawfik Arabi , Grant McFarland , Vivek De
发明人： Siva Narendra , James Tschanz , Victor Zia , Badarinath Kommandur , Tawfik Arabi , Grant McFarland , Vivek De
IPC分类号： G01R31/26
CPC分类号： G01R31/2882 , G01R31/2879
摘要： A method and apparatus are provided for adjusting a frequency of a die. This may include measuring characteristics of a die at various combinations of power supply voltage, body bias voltage and/or temperature and determining operating characteristics, such as power supply voltage and body bias voltage, based on the measured characteristics.
摘要翻译：提供了一种用于调整管芯频率的方法和装置。这可以包括基于所测量的特性，在电源电压，体偏置电压和/或温度的各种组合下测量管芯的特性，并确定诸如电源电压和体偏置电压的操作特性。

118. 发明申请

US20060132218A1 Body biasing methods and circuits 审中-公开
标题翻译：车身偏置方式和电路
公开(公告)号：US20060132218A1
公开(公告)日：2006-06-22
申请号：US11018016
申请日：2004-12-20
申请人： James Tschanz , Siva Narendra , Vivek De
发明人： James Tschanz , Siva Narendra , Vivek De
IPC分类号： H03K3/01
CPC分类号： G05F3/205 , H03K2217/0018
摘要： In some embodiments, a chip is provided that comprises a group of transistors and a body bias generator. The group of transistors is coupled to the body bias generator. The body bias generator is configured to body bias the transistors at a level based on one or more measured parameters associated with the chip and on an operating mode. Other embodiments are disclosed herein and/or are otherwise claimed.
摘要翻译：在一些实施例中，提供了包括一组晶体管和体偏置发生器的芯片。晶体管组耦合到体偏置发生器。身体偏置发生器被配置为基于与芯片相关联的一个或多个测量参数和在操作模式上将晶体管偏置在一个电平上。其他实施方案在此公开和/或以其他方式要求保护。

119. 发明申请

US20060104128A1 Method and apparatus to clamp SRAM supply voltage 有权
公开(公告)号：US20060104128A1
公开(公告)日：2006-05-18
申请号：US11320789
申请日：2005-12-30
申请人： Dinesh Somasekhar , Muhammad Khellah , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
发明人： Dinesh Somasekhar , Muhammad Khellah , Yibin Ye , Vivek De , James Tschanz , Stephen Tang
IPC分类号： G11C7/10
CPC分类号： G11C5/143 , G11C5/147 , G11C11/413
摘要： An apparatus and method are provided for limiting a drop of a supply voltage in an SRAM device to retain the state of the memory during an IDLE state. The apparatus may include a memory array, a sleep device, and a clamping circuit. The clamping circuit may be configured to activate the sleep device when a voltage drop across the memory array falls below a preset voltage and the memory array is in an IDLE state.

120. 发明申请

US20060020838A1 Method, apparatus and system of adjusting one or more performance-related parameters of a processor 有权
标题翻译：调整处理器的一个或多个性能相关参数的方法，装置和系统
公开(公告)号：US20060020838A1
公开(公告)日：2006-01-26
申请号：US10879486
申请日：2004-06-30
申请人： James Tschanz , Stephen Tang , Siva Narendra , Vivek De
发明人： James Tschanz , Stephen Tang , Siva Narendra , Vivek De
IPC分类号： G06F1/26
CPC分类号： G06F1/324 , G06F1/206 , G06F1/3203 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Embodiments of the present invention provide a method, apparatus and system for dynamically adjusting one or more performance-related parameters of a processor core based on at least one operation parameter related to an operating condition of the processor core.
摘要翻译：本发明的实施例提供了一种用于基于与处理器核心的操作条件相关的至少一个操作参数来动态地调整处理器核心的一个或多个与性能有关的参数的方法，装置和系统。

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