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111. 发明授权

US06392430B1 Method of forming coaxial silicon interconnects 失效
标题翻译：用于测试半导体器件的同轴硅互连
公开(公告)号：US06392430B1
公开(公告)日：2002-05-21
申请号：US09722866
申请日：2000-11-27
申请人： Salman Akram , David R. Hembree , Alan G. Wood
发明人： Salman Akram , David R. Hembree , Alan G. Wood
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , G01R1/0408
摘要： An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer and a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon-containing insulation and a metal for shielding the trace from “crosstalk” and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristics matching those of the semiconductor die or wafer and provides clean signals.
摘要翻译：用于测试裸半导体裸片的互连装置包括半导体衬底上的凸起接触构件。接触构件覆盖有绝缘层和通过导电迹线连接到测试电路的导电盖。该迹线覆盖有含硅绝缘体和金属的同轴层，用于屏蔽“串扰”和其他干扰的迹线。用于在晶片上同时测试多个管芯的装置具有与半导体管芯或晶片的热膨胀特性相匹配的热膨胀特性并提供干净的信号。

112. 发明授权

US06340894B1 Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect 失效
标题翻译：半导体测试装置包括具有接触构件的基板和导电聚合物互连
公开(公告)号：US06340894B1
公开(公告)日：2002-01-22
申请号：US08947087
申请日：1997-10-08
申请人： Warren M. Farnworth , Alan G. Wood , Trung Tri Doan , David R. Hembree
发明人： Warren M. Farnworth , Alan G. Wood , Trung Tri Doan , David R. Hembree
IPC分类号： G01R3102
CPC分类号： H05K3/4007 , G01R1/0466 , G01R1/0483 , G01R3/00 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/85 , H01L2224/05554 , H01L2224/05573 , H01L2224/056 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10161 , H01L2924/14 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H01L2924/15174 , H01L2924/15787 , H01L2924/16195 , H05K3/0058 , H05K3/0067 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2924/00 , H01L2224/45099 , H01L2224/05599
摘要： A die contacting substrate establishes ohmic contact with the die by means of raised portions on contact members. The raised portions are dimensioned so that a compression force applied to the die against the substrate results in a limited penetration of the contact member into the bondpads. The arrangement may be used for establishing electrical contact and with a burn-in oven and with a discrete die tester. This permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. A Z-axis anisotropic conductive interconnect material may be interposed between the die attachment surface and the die.
摘要翻译：模具接触衬底通过接触构件上的凸起部分与模具建立欧姆接触。凸起部分的尺寸被设计成使得对模具施加到基板上的压缩力导致接触构件有限地渗透到粘合垫中。该装置可以用于建立电接触以及使用老化烘箱和离散模具测试仪。这允许在组装之前对模具进行表征，从而可以以未包装的形式转移模具。 Z轴各向异性导电互连材料可以插入在模具附接表面和模具之间。

113. 发明授权

US06275052B1 Probe card and testing method for semiconductor wafers 有权
标题翻译：半导体晶圆的探针卡和测试方法
公开(公告)号：US06275052B1
公开(公告)日：2001-08-14
申请号：US09303367
申请日：1999-04-30
申请人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
发明人： David R. Hembree , Warren M. Farnworth , Salman Akram , Alan G. Wood , C. Patrick Doherty , Andrew J. Krivy
IPC分类号： G01R1073
CPC分类号： G01R1/073 , G01R31/2886
摘要： A probe card for testing semiconductor wafers, and a method and system for testing wafers using the probe card are provided. The probe card is configured for use with a conventional testing apparatus, such as a wafer probe handler, in electrical communication with test circuitry. The probe card includes an interconnect substrate having contact members for establishing electrical communication with contact locations on the wafer. The probe card also includes a membrane for physically and electrically connecting the interconnect substrate to the testing apparatus, and a compressible member for cushioning the pressure exerted on the interconnect substrate by the testing apparatus. The interconnect substrate can be formed of silicon with raised contact members having penetrating projections. Alternately the contact members can be formed as indentations for testing bumped wafers. The membrane can be similar to multi layered TAB tape including metal foil conductors attached to a flexible, electrically-insulating, elastomeric tape. The probe card can be configured to contact all of the dice on the wafer at the same time, so that test signals can be electronically applied to selected dice as required.
摘要翻译：提供了用于测试半导体晶片的探针卡，以及使用探针卡测试晶片的方法和系统。探针卡被配置用于与测试电路电连通的常规测试装置，例如晶片探测器处理器。探针卡包括具有用于与晶片上的接触位置建立电连通的接触构件的互连基板。探针卡还包括用于将互连基板物理和电连接到测试装置的膜，以及用于缓冲由测试装置施加在互连基板上的压力的可压缩构件。互连衬底可以由具有穿透突起的凸起接触构件的硅形成。或者，接触构件可以形成为用于测试凸起的晶片的凹陷。膜可以类似于多层TAB带，其包括附接到柔性，电绝缘的弹性体带的金属箔导体。探针卡可以配置为同时接触晶片上的所有骰子，以便测试信号可以根据需要以电子方式应用于选定的骰子。

114. 发明授权

US06222379B1 Conventionally sized temporary package for testing semiconductor dice 失效
标题翻译：用于测试半导体骰子的常规尺寸的临时包装
公开(公告)号：US06222379B1
公开(公告)日：2001-04-24
申请号：US09093357
申请日：1998-06-08
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2863 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/80 , H01L24/85 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.
摘要翻译：提供了一种用于封装和测试半导体管芯的方法。该方法包括形成具有与常规塑料或陶瓷半导体封装相同的尺寸，形状和引线配置的裸片的临时封装。临时包装可用于使用标准设备对模具进行老化测试。然后可以将模具从包装中取出并被认证为已知的好的模具。在说明性实施例中，封装形成为SOJ构造。该包装包括底座，互连和力施加机构。封装基底可以使用陶瓷层压工艺或Cerdip形成工艺由陶瓷或塑料制成。

115. 发明授权

US06215322B1 Conventionally sized temporary package for testing semiconductor dice 失效
公开(公告)号：US06215322B1
公开(公告)日：2001-04-10
申请号：US08888471
申请日：1997-07-07
申请人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
发明人： Warren M. Farnworth , Alan G. Wood , David R. Hembree , Salman Akram
IPC分类号： G01R3102
CPC分类号： G01R1/0466 , G01R1/0483 , G01R3/00 , G01R31/2863 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/48 , H01L24/80 , H01L24/85 , H01L2224/16145 , H01L2224/48 , H01L2224/85001 , H01L2225/06562 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/0105 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H05K3/0058 , H05K3/0067 , H05K3/4007 , H05K3/423 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H01L2224/78 , H01L2224/45099 , H01L2224/05599 , H01L2924/00
摘要： A method for packaging and testing a semiconductor die is provided. The method includes forming a temporary package for the die that has a size, shape and lead configuration that is the same as a conventional plastic or ceramic semiconductor package. The temporary package can be used for burn-in testing of the die using standard equipment. The die can then be removed from the package and certified as a known good die. In an illustrative embodiment the package is formed in a SOJ configuration. The package includes a base, an interconnect and a force applying mechanism. The package base can be formed of ceramic or plastic using a ceramic lamination process or a Cerdip formation process.

116. 发明授权

US06175242B1 Method for forming coaxial silicon interconnects 失效
标题翻译：形成同轴硅互连的方法
公开(公告)号：US06175242B1
公开(公告)日：2001-01-16
申请号：US09467437
申请日：1999-12-20
申请人： Salman Akram , David R. Hembree , Alan G. Wood
发明人： Salman Akram , David R. Hembree , Alan G. Wood
IPC分类号： G01R3102
CPC分类号： G01R31/2886 , G01R1/0408
摘要： An interconnect apparatus for testing bare semiconductor dice comprises raised contact members on a semiconductive substrate. The contact members are covered with an insulation layer and a conductive cap connected by a conductive trace to a testing circuit. The trace is covered with coaxial layers of a silicon containing insulation and a metal for shielding the trace from “cross-talk” and other interference. An apparatus for simultaneous testing of multiple dies on a wafer has thermal expansion characteristics matching those of the semiconductor die or wafer and provides clean signals.
摘要翻译：用于测试裸半导体裸片的互连装置包括半导体衬底上的凸起接触构件。接触构件覆盖有绝缘层和通过导电迹线连接到测试电路的导电盖。该痕迹覆盖有含硅绝缘体和金属的同轴层，用于屏蔽“串扰”和其他干扰的痕迹。用于在晶片上同时测试多个管芯的装置具有与半导体管芯或晶片的热膨胀特性相匹配的热膨胀特性并提供干净的信号。

117. 发明授权

US6072326A System for testing semiconductor components 失效
标题翻译：半导体元件测试系统
公开(公告)号：US6072326A
公开(公告)日：2000-06-06
申请号：US916434
申请日：1997-08-22
申请人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
发明人： Salman Akram , David R. Hembree , Warren M. Farnworth , Derek Gochnour , Alan G. Wood , John O. Jacobson
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0433 , G01R1/0483
摘要： A system and method for testing semiconductor components are provided. The system includes: a test board, sockets mounted to the test board in electrical communication with test circuitry, and carriers mounted to the sockets for housing the components. The carriers include bases, and interconnects mounted thereon, having contact members configured to make temporary electrical connections with contacts on the components. In addition, the contact members on the interconnects can be shaped to perform an alignment function, and to prevent excessive deformation of the contacts on the components. The sockets include camming members and electrical connectors configured to electrically contact the carriers with a zero insertion force. During a test procedure, the bases and interconnects can remain mounted to the sockets on the test board, as the components are aligned and placed in electrical contact with the interconnects. However, different bases and interconnects can be mounted to the sockets for testing different types of components.
摘要翻译：提供了一种用于测试半导体部件的系统和方法。该系统包括：测试板，安装在与测试电路电气通信的测试板上的插座，以及安装到插座以用于容纳部件的载体。载体包括底座和安装在其上的互连件，其具有被配置为与部件上的触点进行临时电连接的接触构件。此外，互连上的接触构件可以成形为执行对准功能，并且防止部件上的触点的过度变形。插座包括凸轮构件和被配置为以零插入力电接触托架的电连接器。在测试过程中，基板和互连件可以保持安装到测试板上的插座上，因为组件对齐并放置成与互连件电接触。然而，可以将不同的基座和互连件安装到插座以测试不同类型的部件。

118. 发明授权

US5896036A Carrier for testing semiconductor dice 失效
标题翻译：载体用于测试半导体骰子
公开(公告)号：US5896036A
公开(公告)日：1999-04-20
申请号：US662414
申请日：1996-06-10
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/75 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R3/00 , G01R31/2863 , H01L2224/16145 , H01L2224/48 , H01L2224/75 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/09701 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A carrier for testing an unpackaged semiconductor die is provided. The carrier includes: a base; a temporary interconnect for establishing electrical communication between the die and external test circuitry; a retention mechanism for securing the interconnect to the base; and a force distribution mechanism for biasing the die and interconnect together. The interconnect includes a substrate having raised contact members adapted to penetrate bond pads, or tests pads, on the die to form an electrical connection. Conductive traces are formed on the substrate in electrical communication with the raised contact members and connect to external connectors formed on the base. The interconnect is adapted for testing a particular type of die but is interchangeable with other interconnects to permit testing of different types of dice using a universal carrier.
摘要翻译：提供了用于测试未封装的半导体管芯的载体。承运人包括：基地; 用于建立管芯和外部测试电路之间的电通信的临时互连; 用于将互连件固定到基座的保持机构; 以及用于偏压模具并互连在一起的力分配机构。互连包括具有凸起的接触构件的衬底，该衬底适于穿过模具上的接合焊盘或测试衬垫以形成电连接。导电迹线形成在与凸起接触构件电连通的基板上，并连接到形成在基座上的外部连接器。互连适用于测试特定类型的管芯，但可与其他互连互换，以允许使用通用载体测试不同类型的管芯。

119. 发明授权

US5878485A Method for fabricating a carrier for testing unpackaged semiconductor dice 失效
标题翻译：制造用于测试未封装的半导体晶片的载体的方法
公开(公告)号：US5878485A
公开(公告)日：1999-03-09
申请号：US615119
申请日：1996-03-13
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R1/04 , G01R1/067 , G01R1/073 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , H01R43/00
CPC分类号： G01R1/0466 , G01R1/0483 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/75 , H01L24/80 , H01L24/85 , H05K3/4007 , G01R3/00 , G01R31/2863 , H01L2224/05553 , H01L2224/16145 , H01L2224/48 , H01L2224/75 , H01L2224/85001 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01023 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01042 , H01L2924/01046 , H01L2924/01047 , H01L2924/01074 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/181 , H01L2924/19041 , H01L2924/30105 , H01L2924/3025 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423 , Y10T29/49117 , Y10T29/49155 , Y10T29/49158 , Y10T29/49172
摘要： A method for fabricating a carrier for testing an unpackaged semiconductor die is provided. The carrier includes a carrier base for supporting the die; an interconnect for establishing a temporary electrical connection with the die; and a force distribution mechanism for biasing the die and interconnect together. In an illustrative embodiment the carrier is formed with a laminated ceramic base. The ceramic base includes internal conductive lines that are wire bonded to the interconnect and metal plated external contacts that are connected to external test circuitry. In an alternate embodiment the carrier is formed with an injection molded plastic base and includes 3-D circuitry formed by a metallization and photolithographic process. In either case, the carrier is adapted for testing different die configurations by interchanging different interconnects.
摘要翻译：提供了一种用于制造用于测试未封装的半导体管芯的载体的方法。载体包括用于支撑模具的载体基体; 用于建立与所述管芯的临时电连接的互连; 以及用于偏压模具并互连在一起的力分配机构。在说明性实施例中，载体形成有层压陶瓷基底。陶瓷基座包括内部导电线，引线连接到互连线和金属电镀外部触点，连接到外部测试电路。在替代实施例中，载体由注射成型的塑料基底形成，并且包括通过金属化和光刻工艺形成的3-D电路。在任一情况下，载体适于通过互换不同的互连来测试不同的管芯配置。

120. 发明授权

US5408190A Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die 失效
标题翻译：具有用于非封装模具的离散模具老化的衬底互连的测试装置
公开(公告)号：US5408190A
公开(公告)日：1995-04-18
申请号：US073005
申请日：1993-06-07
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree
IPC分类号： G01R1/04 , G01R3/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L21/68 , H01L23/13 , H01L23/498 , H05K3/00 , H05K3/40 , H05K3/42 , G01R31/02
CPC分类号： H05K3/4007 , G01R1/0466 , G01R31/2893 , H01L21/6835 , H01L22/20 , H01L23/13 , H01L23/49816 , H01L23/49838 , H01L24/85 , G01R1/0483 , G01R3/00 , G01R31/2863 , H01L2224/05554 , H01L2224/16145 , H01L2224/48091 , H01L2224/48227 , H01L2224/48465 , H01L2224/85001 , H01L2224/85205 , H01L2225/06562 , H01L24/48 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01014 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01075 , H01L2924/01082 , H01L2924/01322 , H01L2924/14 , H01L2924/15151 , H01L2924/15174 , H01L2924/15787 , H01L2924/16195 , H05K2201/0133 , H05K2201/0347 , H05K2201/0367 , H05K2201/0394 , H05K2201/09481 , H05K2201/09563 , H05K2203/0307 , H05K2203/0723 , H05K3/0058 , H05K3/0067 , H05K3/423
摘要： A reusable burn-in/test fixture for discrete die consists of two halves. The first half of the test fixture contains cavity in which die is inserted. Electrical contact with bondpads or bumps on the die is established through an intermediate substrate. When the two halves are assembled, electrical contact with the die is established. The fixture establishes the electrical contact and with a burn-in oven and with a discrete die tester. The test fixture need not be opened until the burn-in and electrical tests are completed. The fixture permits the die to be characterized prior to assembly, so that the die may then be transferred in an unpackaged form. The intermediate substrate may be formed of semiconductor material or of a ceramic insulator. A Z-axis anisotropic conductive interconnect material may be interposed between the intermediate substrate and the die.
摘要翻译：用于离散模具的可重复使用的老化/测试夹具由两半组成。测试夹具的前半部分包含插入模具的腔体。通过中间基板建立与管芯上的焊盘或凸块的电接触。当组装两个半部时，建立与模具的电接触。固定装置建立了电气接触，并配有一个老化烘箱和一个独立的模具测试仪。在老化和电气测试完成之前，测试夹具不需要打开。夹具允许在组装之前对模具进行表征，使得模具然后可以以未包装的形式传送。中间基板可以由半导体材料或陶瓷绝缘体形成。 Z轴各向异性导电互连材料可以介于中间基板和模具之间。

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