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111. 发明授权

US06185705B2 Method and apparatus for checking the resistance of programmable elements 失效
标题翻译：用于检查可编程元件电阻的方法和装置
公开(公告)号：US06185705B2
公开(公告)日：2001-02-06
申请号：US08813525
申请日：1997-03-07
申请人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
发明人： Douglas J. Cutter , Adrian E. Ong , Fan Ho , Kurt D. Beigel , Brett M. Debenham , Dien Luong , Kim Pierce , Patrick J. Mullarkey
IPC分类号： G11C2900
CPC分类号： G11C17/18
摘要： Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.
摘要翻译：公开了用于检查集成电路中的反熔丝元件的电阻的方法和装置。将基于反熔丝元件的电阻的电压与基于已知电阻的电压进行比较，并且生成其二进制值表示反熔丝元件的电阻是否高于或低于已知电阻值的输出信号。该方法和装置在验证反熔丝元件的编程方面是有用的。

112. 再颁专利

USRE36821E Wordline driver circuit having a directly gated pull-down device 失效
标题翻译：字线驱动电路具有直接门控下拉装置
公开(公告)号：USRE36821E
公开(公告)日：2000-08-15
申请号：US644351
申请日：1996-05-10
申请人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
发明人： Stephen L. Casper , Paul S. Zagar , Adrian E. Ong
IPC分类号： G11C8/00 , G11C8/08
CPC分类号： G11C8/08
摘要： The invention is a circuit and method for quickly driving non-selected wordlines to correct potentials. The invention drives the non-selected wordlines to low potentials through a driving device directly gated by a primary select predecode signal generated by decode circuitry. The driving device is electrically interposed between the wordline and a reference node. The invention provides low power operation, and provides reliable wordline selection for circuits having supply potentials less than 5 volts.
摘要翻译：本发明是用于快速驱动未选择的字线以纠正电位的电路和方法。本发明通过由解码电路产生的初级选择预解码信号直接选通的驱动装置将未选择的字线驱动到低电位。驱动装置电插入字线和参考节点之间。本发明提供低功率操作，并且为电源电压低于5伏的电路提供可靠的字线选择。

113. 发明授权

US6031784A Hierarchical decoding of a memory device 有权
标题翻译：存储器件的分层解码
公开(公告)号：US6031784A
公开(公告)日：2000-02-29
申请号：US148817
申请日：1998-09-04
申请人： Adrian E. Ong
发明人： Adrian E. Ong
IPC分类号： G11C7/18 , G11C8/14 , G11C7/00
CPC分类号： G11C7/18 , G11C8/14
摘要： In one aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line for accessing a memory cell. A local word line driver, which drives the local word line, has at most two transistors, each of these transistors coupled to the local word line. In another aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line driver for driving a local word line. A local phase line driver is connected to the local word line driver by a single metal line. The local phase line driver cooperates with the local word line driver for accessing a memory cell.
摘要翻译：在本发明的一个方面，用于存储器件的分层解码的电路包括用于访问存储器单元的本地字线。驱动本地字线的本地字线驱动器具有至多两个晶体管，这些晶体管中的每一个耦合到本地字线。在本发明的另一方面，用于存储器件的分层解码的电路包括用于驱动本地字线的本地字线驱动器。局部相线驱动器通过单个金属线连接到本地字线驱动器。本地相线驱动器与本地字线驱动器协作以访问存储单元。

114. 发明授权

US5970008A Efficient method for obtaining usable parts from a partially good memory integrated circuit 失效
公开(公告)号：US5970008A
公开(公告)日：1999-10-19
申请号：US993824
申请日：1997-12-18
申请人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
发明人： Paul S. Zagar , Brent Keeth , Adrian E. Ong
IPC分类号： G06F12/16 , G01R31/30 , G06F11/22 , G11C29/00 , G11C29/02 , G11C29/04 , G11C29/44 , G11C29/50 , G11C7/00
CPC分类号： G11C29/70 , G01R31/3004 , G06F11/22 , G11C29/02 , G11C29/44 , G11C29/50 , G11C29/83 , G11C29/832 , G11C29/88 , G11C11/401 , G11C2029/5006
摘要： An integrated circuit memory device has multiple subarray partitions which can be independently isolated from the remaining circuitry on the integrated circuit. Subarrays of the integrated circuit can be independently tested. Should a subarray of the integrated circuit be found inoperable it is electrically isolated from the remaining circuitry on the integrated circuit so that it cannot interfere with the normal operation of the remaining circuitry. Defects such as power to ground shorts in a subarray which would have previously been catastrophic can be electrically isolated allowing the remaining functional subarrays to be utilized. Integrated circuit repair by isolation of inoperative elements eliminates the current draw and other performance degradations that have previously been associated with integrated circuits with defects repaired through the incorporation of redundant elements alone.

115. 发明授权

US5631862A Self current limiting antifuse circuit 失效
标题翻译：自限流反熔丝电路
公开(公告)号：US5631862A
公开(公告)日：1997-05-20
申请号：US611419
申请日：1996-03-05
申请人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien S. Luong , Brett Debenham , Kim M. Pierce
发明人： Douglas J. Cutter , Kurt D. Beigel , Adrian E. Ong , Fan Ho , Patrick J. Mullarkey , Dien S. Luong , Brett Debenham , Kim M. Pierce
IPC分类号： G11C17/18 , G11C17/16
CPC分类号： G11C17/18
摘要： An antifuse bank includes a bank of self-decoupling antifuse circuits. The antifuse circuits are programmed according to a pattern of address bits by blowing antifuses corresponding to bits of the address. The antifuses are blown by applying a high voltage across the antifuse. As each antifuse is blown, its resistance drops and current through the antifuse increases. The self-decoupling circuit detects the increased current flow and, when the antifuse resistance is sufficiently low, limits current flow through the antifuse. The antifuse thus does not load the high voltage source as other antifuses are blown.
摘要翻译：反熔丝库包括一组自解耦反熔丝电路。反熔丝电路根据地址位的模式通过吹出与地址的位相对应的反熔丝来编程。通过在反熔丝上施加高电压来吹制反熔丝。当每个反熔丝熔断时，其电阻下降，并且通过反熔丝的电流增加。自解耦电路检测到增加的电流，并且当反熔丝电阻足够低时，限制了通过反熔丝的电流流动。因此，反熔丝因其他反熔丝被吹制而不加载高压源。

116. 发明授权

US5488583A Memory integrated circuits having on-chip topology logic driver, and methods for testing and producing such memory integrated circuits 失效
标题翻译：具有片上拓扑逻辑驱动器的存储器集成电路，以及用于测试和产生这种存储器集成电路的方法
公开(公告)号：US5488583A
公开(公告)日：1996-01-30
申请号：US311582
申请日：1994-09-22
申请人： Adrian E. Ong , William K. Waller , Paul S. Zagar
发明人： Adrian E. Ong , William K. Waller , Paul S. Zagar
IPC分类号： G11C7/10 , G11C7/18 , G11C29/36 , G11C7/00 , G11C29/00
CPC分类号： G11C29/36 , G11C7/1006 , G11C7/18
摘要： A memory integrated circuit chip of a predefined circuit topology has an on-chip topology logic driver. The topology logic driver selectively inverts data being written to and read from addressed memory cells in the memory IC based upon location of the addressed memory cells in the circuit topology of the memory array. The topology logic driver is preferably a logic circuit that embodies a boolean function defining the circuit topology. A method for testing and producing such memory ICs is also described.
摘要翻译：预定义电路拓扑的存储器集成电路芯片具有片上拓扑逻辑驱动器。拓扑逻辑驱动器基于存储器阵列的电路拓扑中寻址的存储器单元的位置选择性地反转正在写入存储器IC中的寻址存储器单元的数据和从其读出的数据。拓扑逻辑驱动器优选地是实现定义电路拓扑的布尔函数的逻辑电路。还描述了用于测试和产生这种存储器IC的方法。

117. 发明授权

US5465232A Sense circuit for tracking charge transfer through access transistors in a dynamic random access memory 失效
标题翻译：用于跟踪通过动态随机存取存储器中的存取晶体管的电荷转移的感测电路
公开(公告)号：US5465232A
公开(公告)日：1995-11-07
申请号：US275890
申请日：1994-07-15
申请人： Adrian E. Ong , Paul S. Zagar
发明人： Adrian E. Ong , Paul S. Zagar
IPC分类号： G11C11/409 , G11C11/407 , G11C11/4091 , G11C11/4094 , G11C11/40
CPC分类号： G11C11/4094 , G11C11/4091
摘要： A simple, low-power sense circuit is disclosed that accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line. The circuit, which is preferably located in the peripheral circuitry, employs a model access transistor to charge a pull-up node that is coupled to ground through a capacitor which simulates digit line capacitance. The pull-up node is coupled to the gate of a N-channel field-effect output transistor. When voltage on the node reaches the threshold voltage of the output transistor, the output transistor begins to turn on. The output from the output transistor (in this case, ground potential) is fed back to the gate of a P-channel device which couples the node to V.sub.CC. The P-channel device is used to pull up the node to V.sub.CC rapidly once the trip point (i.e., the threshold voltage) of the N-channel output transistor is reached. The sense circuit is reset for the next read cycle by sending a high signal to the gate of an N-channel reset transistor, which couples the capacitive node to ground.
摘要翻译：公开了一种简单的低功率检测电路，其精确地跟踪动态随机存取存储器单元的电容器与其相关的数字线之间的电荷转移。优选地位于外围电路中的电路采用模型存取晶体管，以通过模拟数字线电容的电容器耦合到地的上拉节点。上拉节点耦合到N沟道场效应输出晶体管的栅极。当节点上的电压达到输出晶体管的阈值电压时，输出晶体管开始导通。输出晶体管（在这种情况下为接地电位）的输出反馈到将节点耦合到VCC的P沟道器件的栅极。一旦达到N沟道输出晶体管的跳变点（即阈值电压），P沟道器件用于将节点快速上拉至VCC。通过向N沟道复位晶体管的栅极发送高信号，将感测电路复位为下一个读取周期，N沟道复位晶体管将电容节点耦合到地。

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