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101. 发明授权

US06867143B1 Method for etching a semiconductor substrate using germanium hard mask 失效
标题翻译：使用锗硬掩模蚀刻半导体衬底的方法
公开(公告)号：US06867143B1
公开(公告)日：2005-03-15
申请号：US09599783
申请日：2000-06-22
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L. Ma
IPC分类号： C23F4/00 , C23G1/00 , H01L21/302 , H01L21/308 , H01L21/3213
CPC分类号： H01L21/3081 , C23F4/00 , C23G1/00 , H01L21/3086 , H01L21/32134
摘要： An etching process using germanium hard mask (25) includes forming a dielectric layer (15) over a major surface (11) of a semiconductor substrate (10) and depositing a metallic germanium layer (22) over the dielectric layer (15). The metallic germanium layer (22) is patterned through a photo resist (24) to form the germanium hard mask (25). The dielectric layer (15) is selectively etched through the germanium hard mask (25) to form a dielectric hard mask (35), through which the semiconductor substrate (10) is subsequently etched. After forming the dielectric hard mask (35), the germanium hard mask (25) is stripped away by oxidizing the metallic germanium hard mask (25) to transform it into a layer (27) of germanium oxide and rinsing the semiconductor substrate (10) in water to remove the germanium oxide layer (27). Preferably, the germanium hard mask (25) is removed before etching the semiconductor substrate (10).
摘要翻译：使用锗硬掩模（25）的蚀刻工艺包括在半导体衬底（10）的主表面（11）上形成电介质层（15），并在电介质层（15）上沉积金属锗层（22）。通过光致抗蚀剂（24）将金属锗层（22）图案化以形成锗硬掩模（25）。通过锗硬掩模（25）选择性地蚀刻电介质层（15）以形成电介质硬掩模（35），随后蚀刻半导体衬底（10）。在形成电介质硬掩模（35）之后，通过氧化金属锗硬掩模（25）将锗硬掩模（25）剥离，将其转化成氧化锗层（27）并冲洗半导体衬底（10），在水中以除去氧化锗层（27）。优选地，在蚀刻半导体衬底（10）之前去除锗硬掩模（25）。

102. 发明授权

US08568604B2 CMOS gate structures fabricated by selective oxidation 有权
标题翻译：通过选择性氧化制造的CMOS栅极结构
公开(公告)号：US08568604B2
公开(公告)日：2013-10-29
申请号：US12186075
申请日：2008-08-05
申请人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Bruce B. Doris , Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： B44C1/22 , H01L21/302
CPC分类号： H01L21/32139 , H01L21/0337 , H01L21/0338 , H01L21/823828 , H01L21/823864
摘要： A sidewall image transfer process for forming sub-lithographic structures employs a layer of sacrificial material that is deposited over a structure layer and covered by a cover layer. The sacrificial material layer and the cover layer are patterned with conventional resist and etched to form a sacrificial mandrel. The edges of the mandrel are oxidized or nitrided in a plasma at low temperature, after which the material layer and the cover layer are stripped, leaving sublithographic sidewalls. The sidewalls are used as hardmasks to etch sublithographic gate structures in the gate conductor layer.
摘要翻译：用于形成亚光刻结构的侧壁图像转印工艺采用沉积在结构层上并被覆盖层覆盖的牺牲材料层。牺牲材料层和覆盖层用常规抗蚀剂图案化并蚀刻以形成牺牲芯棒。心轴的边缘在低温下在等离子体中被氧化或氮化，之后剥离材料层和覆盖层，留下亚光刻的侧壁。侧壁用作硬掩模来蚀刻栅极导体层中的亚光刻栅极结构。

103. 发明申请

US20090014767A1 CARBON NANOTUBE CONDUCTOR FOR TRENCH CAPACITORS 有权
标题翻译：用于TRENCH电容器的碳纳米管导体
公开(公告)号：US20090014767A1
公开(公告)日：2009-01-15
申请号：US10596022
申请日：2003-12-18
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III , Larry A. Nesbit
IPC分类号： H01L27/108
CPC分类号： H01L27/10864 , B82Y10/00 , H01L27/10861 , Y10S977/936 , Y10S977/943 , Y10S977/948
摘要： A trench-type storage device includes a trench in a substrate (100), with bundles of carbon nanotubes (202) lining the trench and a trench conductor (300) filling the trench. A trench dielectric (200) may be formed between the carbon nanotubes and the sidewall of the trench. The bundles of carbon nanotubes form an open cylinder structure lining the trench. The device is formed by providing a carbon nanotube catalyst structure on the substrate and patterning the trench in the substrate; the carbon nanotubes are then grown down into the trench to line the trench with the carbon nanotube bundles, after which the trench is filled with the trench conductor.
摘要翻译：沟槽式存储装置包括在衬底（100）中的沟槽，具有衬在沟槽上的碳纳米管（202）的束和填充沟槽的沟槽导体（300）。可以在碳纳米管和沟槽的侧壁之间形成沟槽电介质（200）。碳纳米管束形成在沟槽内衬的开放圆筒结构。该器件通过在衬底上提供碳纳米管催化剂结构并对衬底中的沟槽进行图案化而形成; 然后将碳纳米管向下生长到沟槽中以与碳纳米管束对准沟槽，然后用沟槽导体填充沟槽。

104. 发明授权

US07385673B2 Immersion lithography with equalized pressure on at least projection optics component and wafer 有权
标题翻译：至少在投影光学部件和晶片上具有均衡压力的浸没光刻
公开(公告)号：US07385673B2
公开(公告)日：2008-06-10
申请号：US11160156
申请日：2005-06-10
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Peter H. Mitchell
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Peter H. Mitchell
IPC分类号： G03B27/42
CPC分类号： G03F7/70341
摘要： An immersion lithography apparatus and method, and a lithographic optical column structure are disclosed for conducting immersion lithography with at least the projection optics of the optical system and the wafer in different fluids at the same pressure. In particular, an immersion lithography apparatus is provided in which a supercritical fluid is introduced about the wafer, and another fluid, e.g., an inert gas, is introduced to at least the projection optics of the optical system at the same pressure to alleviate the need for a special lens. In addition, the invention includes an immersion lithography apparatus including a chamber filled with a supercritical immersion fluid and enclosing a wafer to be exposed and at least a projection optic component of the optical system.
摘要翻译：公开了一种浸没式光刻设备和方法以及平版印刷光学柱结构，用于在相同压力下用不同流体中的光学系统和晶片的至少投影光学器件进行浸没光刻。特别地，提供了一种浸没式光刻设备，其中超临界流体被引入晶片周围，并且另一种流体（例如惰性气体）在相同的压力下被引入光学系统的至少投影光学器件以减轻需要用于特殊镜头。此外，本发明包括浸没式光刻设备，其包括填充有超临界浸没流体的腔室并且封装要暴露的晶片和至少光学系统的投影光学部件。

105. 发明申请

US20080128811A1 SEMICONDUCTOR DEVICES WITH BURIED ISOLATION REGIONS 审中-公开
标题翻译：带有分离隔离区的半导体器件
公开(公告)号：US20080128811A1
公开(公告)日：2008-06-05
申请号：US12018886
申请日：2008-01-24
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger
IPC分类号： H01L29/786
CPC分类号： H01L29/0653 , B82Y10/00 , H01L21/28114 , H01L21/3086 , H01L21/31144 , H01L21/76224 , H01L21/76243 , H01L21/76267 , H01L21/76283 , H01L29/0649 , H01L29/0657 , H01L29/1083 , H01L29/165 , H01L29/66545 , H01L29/66575 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78654 , H01L29/78684
摘要： Semiconductor structures and method of forming semiconductor structures. The semiconductor structures including nano-structures or fabricated using nano-structures. The method of forming semiconductor structures including generating nano-structures using a nano-mask and performing additional semiconductor processing steps using the nano-structures generated.
摘要翻译：半导体结构和形成半导体结构的方法。包括纳米结构或使用纳米结构制造的半导体结构。形成半导体结构的方法包括使用纳米掩模生成纳米结构，并使用所生成的纳米结构进行附加的半导体加工步骤。

106. 发明授权

US07271079B2 Method of doping a gate electrode of a field effect transistor 失效
标题翻译：掺杂场效应晶体管的栅电极的方法
公开(公告)号：US07271079B2
公开(公告)日：2007-09-18
申请号：US10907569
申请日：2005-04-06
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , Charles W. Koburger, III
IPC分类号： H01L21/425
CPC分类号： H01L29/4983 , H01L29/4908 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/78621 , Y10S977/742 , Y10S977/847
摘要： A method of fabricating a structure and fabricating related semiconductor transistors and novel semiconductor transistor structures. The method of fabricating the structure includes: providing a substrate having a top surface; forming an island on the top surface of the substrate, a top surface of the island parallel to the top surface of the substrate, a sidewall of the island extending between the top surface of the island and the top surface of the substrate; forming a plurality of carbon nanotubes on the sidewall of the island; and performing an ion implantation, the ion implantation penetrating into the island and blocked from penetrating into the substrate in regions of the substrate masked by the island and the carbon nanotubes.
摘要翻译：一种制造结构并制造相关半导体晶体管和新型半导体晶体管结构的方法。制造该结构的方法包括：提供具有顶表面的基底; 在所述基板的顶表面上形成岛，所述岛的顶表面平行于所述基底的顶表面，所述岛的侧壁在所述岛的顶表面和所述基底的顶表面之间延伸; 在岛的侧壁上形成多个碳纳米管; 并且进行离子注入，所述离子注入在所述岛状体和所述碳纳米管所掩盖的基板的区域中贯穿所述岛并阻止其侵入到所述基板内。

107. 发明授权

US06995051B1 Irradiation assisted reactive ion etching 失效
标题翻译：照射辅助反应离子蚀刻
公开(公告)号：US06995051B1
公开(公告)日：2006-02-07
申请号：US10904200
申请日：2004-10-28
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
IPC分类号： H01L21/00
CPC分类号： B23K26/0661 , B23K26/18 , H01J37/32339 , H01L21/3065 , H01L29/66795
摘要： Etching methods and apparatus are disclosed for irradiation assisted reactive ion etching. One embodiment includes providing a substrate having a patterned mask thereon with an exposed area; forming an etch area in the substrate by implanting the exposed area of the substrate with a reactive species; and (laser) irradiating the etch area to volatilize the etch area. The methods modify etch conditions such that they approximate an ‘atomic layer etching’ process, in which thin layers of substrate are selectively and successively etched.
摘要翻译：公开了用于照射辅助反应离子蚀刻的蚀刻方法和装置。一个实施例包括提供具有其上具有曝光区域的图案化掩模的衬底; 通过用反应性物质注入所述衬底的暴露区域来在所述衬底中形成蚀刻区域; 和（激光）照射蚀刻区域以使蚀刻区域挥发。该方法修改蚀刻条件使得它们近似于“原子层蚀刻”工艺，其中选择性地并且连续蚀刻薄层的衬底。

108. 发明授权

US06924200B2 Methods using disposable and permanent films for diffusion and implantation doping 失效
标题翻译：使用一次性和永久性膜进行扩散和注入掺杂的方法
公开(公告)号：US06924200B2
公开(公告)日：2005-08-02
申请号：US10222035
申请日：2002-08-16
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H-L Ma , Patricia M. Marmillion , Donald W. Rakowski
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8238 , H01L21/302 , H01L21/21
CPC分类号： H01L29/6659 , H01L21/2254 , H01L21/2255 , H01L21/823814 , H01L21/823842 , H01L29/665
摘要： Methods are provided that use disposable and permanent films to dope underlying layers through diffusion. Additionally, methods are provided that use disposable films during implantation doping and that provide a surface from which to dope underlying materials. Some of these disposable films can be created from a traditionally non-disposable film and made disposable. In this manner, solvents may be used that do not etch underlying layers of silicon-based materials. Preferably, deep implantation is performed to form source/drain regions, then an anneal step is performed to activate the dopants. A conformal layer is deposited and implanted with dopants. One or more anneal steps are performed to create very shallow extensions in the source/drain regions.
摘要翻译：提供了使用一次性和永久性膜通过扩散来掺杂下层的方法。此外，提供了在植入掺杂期间使用一次性膜的方法，并且提供了用于涂覆下层材料的表面。这些一次性膜中的一些可以由传统的非一次性膜制成并制成一次性的。以这种方式，可以使用不蚀刻硅基材料的下层的溶剂。优选地，进行深度注入以形成源极/漏极区域，然后执行退火步骤以激活掺杂剂。沉积保形层并用掺杂剂注入。执行一个或多个退火步骤以在源极/漏极区域中产生非常浅的延伸。

109. 发明授权

US06919277B2 Deliberate semiconductor film variation to compensate for radial processing differences, determine optimal device characteristics, or produce small productions 失效
标题翻译：有意识的半导体膜变化以补偿径向处理差异，确定最佳器件特性或产生小的生产
公开(公告)号：US06919277B2
公开(公告)日：2005-07-19
申请号：US10707937
申请日：2004-01-27
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak
IPC分类号： C23C16/04 , C23C16/513 , C23C16/52 , H01L21/3105 , H01L21/311 , H01L21/3213 , H01L21/66 , H01L21/762 , H01L21/8234
CPC分类号： H01L22/20 , C23C16/04 , C23C16/513 , C23C16/52 , H01L21/31053 , H01L21/31116 , H01L21/32137 , H01L21/76229 , H01L21/8234 , Y10S438/911
摘要： Methods and apparatuses are disclosed that can introduce deliberate semiconductor film variation during semiconductor manufacturing to compensate for radial processing differences, to determine optimal device characteristics, or produce small production runs. The present invention radially varies the thickness and/or composition of a semiconductor film to compensate for a known radial variation in the semiconductor film that is caused by performing a subsequent semiconductor processing step on the semiconductor film.
摘要翻译：公开了可以在半导体制造期间引入有意的半导体膜变化以补偿径向处理差异，确定最佳器件特性或产生小的生产运行的方法和装置。本发明径向地改变半导体膜的厚度和/或组成，以补偿半导体膜中已知的径向变化，这是通过在半导体膜上执行随后的半导体处理步骤引起的。

110. 发明授权

US06596597B2 Method of manufacturing dual gate logic devices 失效
标题翻译：制造双门逻辑器件的方法
公开(公告)号：US06596597B2
公开(公告)日：2003-07-22
申请号：US09879590
申请日：2001-06-12
申请人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
发明人： Toshiharu Furukawa , Mark C. Hakey , Steven J. Holmes , David V. Horak , William H. Ma
IPC分类号： H01L21336
CPC分类号： H01L29/66484 , H01L21/2807 , H01L29/7831 , H01L29/78645 , H01L29/78648
摘要： The present invention features double- or dual-gate logic devices that contain gate conductors that are consistently self-aligned and that have channels that are of constant width. The inventive process also provides a method of selectively etching germanium-containing gate conductor materials without significantly etching the adjacent silicon channel material. In this manner, the gate conductor can be encased in a dielectric shell without changing the length of the silicon channel. A single-crystal silicon wafer is utilized as the channel material. Pillars or stacks of self aligned dual gate MOSFETs are generated by etching, via the juxtaposition of overlapping germanium-containing gate conductor regions. Vertically etching through regions of both gate conducting material and dielectric insulating material provides an essentially perfect, self-aligned dual gate stack. A process is described wherein the gate conductor material can be selectively etched without etching the channel material.
摘要翻译：本发明的特征在于双栅极或双栅极逻辑器件，其包含一致的自对准并且具有恒定宽度的沟道的栅极导体。本发明的方法还提供了选择性地蚀刻含锗栅极导体材料而不显着蚀刻相邻硅沟道材料的方法。以这种方式，可以将栅极导体封装在电介质壳体中而不改变硅沟道的长度。采用单晶硅晶片作为通道材料。自对准双栅极MOSFET的支柱或堆叠通过通过重叠的含锗栅极导体区域的并置进行蚀刻而产生。通过栅极导电材料和介电绝缘材料的两个区域的垂直蚀刻提供了基本上完美的自对准双栅极叠层。描述了其中可以选择性地蚀刻栅极导体材料而不蚀刻沟道材料的工艺。

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