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101. 发明授权

US06261908B1 Buried local interconnect 失效
标题翻译：埋地方互联
公开(公告)号：US06261908B1
公开(公告)日：2001-07-17
申请号：US09123177
申请日：1998-07-27
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21336
CPC分类号： H01L23/535 , H01L21/76895 , H01L2924/0002 , H01L2924/00
摘要： A method of fabricating a buried local interconnect in a substrate and an integrated circuit incorporating the same are provided. The method includes the steps forming a trench in the substrate and forming a first insulating layer in the trench. A conductor layer is formed on the first insulating layer. A portion of the conductor layer is removed to define a local interconnect layer and a second insulating layer is formed in the trench covering the local interconnect layer. The method provides for a local interconnect layer buried beneath a dielectric layer of an integrated circuit, such as a shallow trench isolation layer. Areas of a substrate above the silicon-silicon dioxide interface formerly reserved for local interconnect layers in conventional processing may now be used for additional conductor lines.
摘要翻译：提供了一种在衬底中制造掩埋局部互连的方法和包括其的集成电路。该方法包括在衬底中形成沟槽并在沟槽中形成第一绝缘层的步骤。导体层形成在第一绝缘层上。去除导体层的一部分以限定局部互连层，并且在覆盖局部互连层的沟槽中形成第二绝缘层。该方法提供了埋在诸如浅沟槽隔离层的集成电路的介电层下面的局部互连层。以前用于常规处理中的局部互连层的硅 - 二氧化硅界面上方的衬底区域现在可用于附加的导体线。

102. 发明授权

US06251800B1 Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance 失效
标题翻译：使用低功率，低压PECVD的超薄沉积栅介质形成，以改善半导体器件性能
公开(公告)号：US06251800B1
公开(公告)日：2001-06-26
申请号：US09227513
申请日：1999-01-06
申请人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
发明人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C23C16/402 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/28194 , H01L21/31612
摘要： An ultrathin gate dielectric and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A low-power, low-pressure plasma-enhanced chemical vapor deposition (PECVD) method employing silane and nitrous oxide sources is used to deposit the dielectric. As compared to conventional PECVD deposition, the method uses lower silane and nitrous oxide flow rates, a more dilute silane in nitrogen mixture, a lower chamber pressure, and a lower radio frequency power density. These settings allow plasma conditions to stabilize so that deposition may be performed in time increments at least as short as 0.1 second, so that oxide thicknesses at least as small as one angstrom may be controllably deposited. The oxide is preferably deposited in portions at multiple substrate mounting positions in a deposition chamber. Combination of oxide portions in this manner is believed to reduce the density of pinholes in the oxide, and the low-power, low-pressure deposition conditions are further believed to reduce plasma damage to the oxide and reduce the density of trap states in the oxide. A rapid thermal anneal of the oxide may be performed after deposition, and may improve the quality of the interface between the oxide and the underlying semiconductor substrate.
摘要翻译：提供一种超薄栅极电介质及其形成方法。认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。使用采用硅烷和一氧化二氮源的低功率，低压等离子体增强化学气相沉积（PECVD）方法沉积电介质。与传统的PECVD沉积相比，该方法使用较低的硅烷和一氧化二氮流率，氮混合物中更稀的硅烷，较低的室压力和较低的射频功率密度。这些设置允许等离子体条件稳定，使得可以以至少短至0.1秒的时间增量执行沉积，使得至少小至一埃的氧化物厚度可以可控地沉积。优选在沉积室中的多个基板安装位置处部分地沉积氧化物。认为以这种方式组合氧化物部分可以降低氧化物中针孔的密度，并且进一步认为低功率，低压沉积条件可减少对氧化物的等离子体损伤并降低氧化物中陷阱态的密度。可以在沉积之后进行氧化物的快速热退火，并且可以提高氧化物和下面的半导体衬底之间的界面的质量。

103. 发明授权

US06245638B1 Trench and gate dielectric formation for semiconductor devices 有权
标题翻译：用于半导体器件的沟槽和栅极电介质形成
公开(公告)号：US06245638B1
公开(公告)日：2001-06-12
申请号：US09128235
申请日：1998-08-03
申请人： Mark I. Gardner , H. Jim Fulford , Charles E. May
发明人： Mark I. Gardner , H. Jim Fulford , Charles E. May
IPC分类号： H01L2176
CPC分类号： H01L21/76224 , H01L21/823462 , H01L21/823481 , Y10S148/05
摘要： Semiconductor device fabrication techniques which integrate the formation of trench isolation areas and gate insulating layers are provided. The fabrication techniques include forming one or more sacrificial layers, such as nitrided oxide layers, over regions of the substrate adjacent to a trench isolation region. The sacrificial layers are then removed prior to gate insulating layer formation. The formation of the sacrificial layers improves the trench structure and also improves the substrate surface for the subsequent formation of the gate insulating layer and gate electrode.
摘要翻译：提供集成沟槽隔离区域和栅极绝缘层的形成的半导体器件制造技术。制造技术包括在与沟槽隔离区相邻的衬底的区域上形成一个或多个牺牲层，例如氮化氧化物层。然后在形成栅极绝缘层之前去除牺牲层。牺牲层的形成改善了沟槽结构，并且还改善了衬底表面，以便随后形成栅极绝缘层和栅电极。

104. 发明授权

US06242317B1 High quality isolation structure formation 有权
标题翻译：高品质的隔离结构形成
公开(公告)号：US06242317B1
公开(公告)日：2001-06-05
申请号：US09264103
申请日：1999-03-08
申请人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
发明人： Mark I. Gardner , Thien T. Nguyen , Charles E. May
IPC分类号： H01L2176
CPC分类号： H01L21/76224
摘要： A method is provided for fabricating an isolation structure, the method including forming a first dielectric layer above a structure and forming an opening in the first dielectric layer and the structure, the opening having sidewalls and a bottom. The method also includes forming a second dielectric layer within the opening on a first portion of the sidewalls and above the bottom of the opening. The method further includes forming a third dielectric layer within the opening adjacent the second dielectric layer and on a second portion of the sidewalls of the opening. The method also further includes passivating bonds in the third dielectric layer to reduce charge-trapping in the third dielectric layer, forming dielectric spacers within the opening adjacent the third dielectric layer and forming a dielectric filler within the opening adjacent the dielectric spacers and above the third dielectric layer.
摘要翻译：提供了一种用于制造隔离结构的方法，所述方法包括在结构上形成第一介电层，并在第一介电层和结构中形成开口，该开口具有侧壁和底部。该方法还包括在侧壁的第一部分和开口的底部之上的开口内形成第二电介质层。该方法还包括在邻近第二电介质层的开口内和在开口的侧壁的第二部分上形成第三电介质层。该方法还包括钝化第三电介质层中的键，以减少第三电介质层中的电荷捕获，在与第三电介质层相邻的开口内形成电介质间隔物，并在邻近电介质间隔物的开口内形成电介质填料，电介质层。

105. 发明授权

US06207485B1 Integration of high K spacers for dual gate oxide channel fabrication technique 失效
标题翻译：用于双栅极氧化物沟道制造技术的高K间隔物的集成
公开(公告)号：US06207485B1
公开(公告)日：2001-03-27
申请号：US09002725
申请日：1998-01-05
申请人： Mark I. Gardner , H. James Fulford , Charles E. May
发明人： Mark I. Gardner , H. James Fulford , Charles E. May
IPC分类号： H01L218238
CPC分类号： H01L21/28185 , H01L21/28202 , H01L21/28211 , H01L29/42368 , H01L29/518 , H01L29/66583
摘要： A semiconductor device has gate with a first material having a first dielectric constant adjacent the semiconductor substrate and a second material having a second dielectric constant adjacent the semiconductor substrate. A conductor, such as polysilicon, is then placed on the gate so that the first and second materials are sandwiched between the conductor and the semiconductor substrate. Since the dielectric constants of the two materials are different, the gate acts like a gate having a single dielectric with at least two thicknesses. This is due to the fact that each material has a dielectric constant that is different. One dielectric constant is larger than the other dielectric constant. The higher dielectric constant material is comprised of two spacers at the sidewalls of the gate. A layer of silicon dioxide is positioned on the semiconductor substrate between the spacers. The thickness of the spacers can be adjusted to optimize the performance of the semiconductor device.
摘要翻译：半导体器件具有栅极，第一材料具有邻近半导体衬底的第一介电常数和邻近半导体衬底的具有第二介电常数的第二材料。然后将诸如多晶硅的导体放置在栅极上，使得第一和第二材料夹在导体和半导体衬底之间。由于两种材料的介电常数不同，栅极的作用就像具有至少两个厚度的单个电介质的栅极。这是由于每种材料的介电常数不同。一个介电常数大于另一介电常数。较高介电常数材料由栅极侧壁上的两个间隔物组成。二氧化硅层位于半导体衬底上的间隔物之间。可以调整间隔件的厚度以优化半导体器件的性能。

106. 发明授权

US6151119A Apparatus and method for determining depth profile characteristics of a dopant material in a semiconductor device 失效
标题翻译：用于确定半导体器件中的掺杂剂材料的深度分布特性的装置和方法
公开(公告)号：US6151119A
公开(公告)日：2000-11-21
申请号：US995022
申请日：1997-12-19
申请人： Alan Campion , Charles E. May , Tim Z. Hossain
发明人： Alan Campion , Charles E. May , Tim Z. Hossain
IPC分类号： G01B11/06 , G01N21/65 , H01L21/66 , G01N21/00
CPC分类号： G01N21/65 , G01B11/0666 , H01L22/12
摘要： An apparatus and method for the determination of a depth profile and/or one or more depth profile characteristics of a dopant material in a semiconductor device includes a light source which can illuminate the device at two or more illumination wavelengths, a detector that receives scattered light from the semiconductor device and determines an intensity characteristic for one or more Raman spectral lines attributable to the presence of the dopant material in the semiconductor device. The intensity characteristics of the Raman spectral lines can then be used to determine the depth profile or depth profile characteristics using profile constants measured from known samples at each of the illumination wavelengths. This apparatus and method can be used in-line because it is noninvasive, relatively quick, and nondestructive.
摘要翻译：用于确定半导体器件中的掺杂剂材料的深度分布和/或一个或多个深度分布特性的装置和方法包括可以以两个或更多个照明波长照亮所述器件的光源，接收散射光的检测器并且确定归因于半导体器件中的掺杂剂材料的存在的一个或多个拉曼光谱线的强度特性。然后可以使用拉曼光谱线的强度特性来使用在每个照明波长处从已知样品测量的分布常数来确定深度分布或深度分布特征。该装置和方法可以在线使用，因为它是非侵入性的，相对快速的和非破坏性的。

107. 发明授权

US6140674A Buried trench capacitor 失效
标题翻译：埋沟电容器
公开(公告)号：US6140674A
公开(公告)日：2000-10-31
申请号：US123117
申请日：1998-07-27
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/334 , H01L21/762 , H01L27/06 , H01L29/94 , H01L29/78 , H01L29/04
CPC分类号： H01L29/66181 , H01L21/76224 , H01L27/0623 , H01L29/945
摘要： An integrated circuit and a method of making the same are provided. The circuit includes a substrate that has a trench formed therein defining and isolating first and second active area and an upper surface. The circuit includes a capacitor that has a first insulating layer formed in the trench, a conductor layer formed on the first insulating layer, and a second insulating layer formed on the first insulating layer that fills the trench. The conductor layer is positioned substantially at or below the upper surface. The circuit integrates trench isolation structure with a capacitor that may be used as a filter between power and ground. The method integrates capacitor formation with trench isolation formation.
摘要翻译：提供集成电路及其制造方法。电路包括具有形成在其中的沟槽的衬底，其限定并隔离第一和第二有源区域和上表面。该电路包括具有形成在沟槽中的第一绝缘层的电容器，形成在第一绝缘层上的导体层，以及形成在填充沟槽的第一绝缘层上的第二绝缘层。导体层基本上位于上表面或下表面。该电路将沟槽隔离结构与可用作电源和地之间的滤波器的电容器集成。该方法集成了具有沟槽隔离形成的电容器形成。

108. 发明授权

US6130012A Ion beam milling to generate custom reticles 有权
标题翻译：离子束铣削生成定制的光罩
公开(公告)号：US6130012A
公开(公告)日：2000-10-10
申请号：US229710
申请日：1999-01-13
申请人： Charles E. May , Thomas J. Goodwin
发明人： Charles E. May , Thomas J. Goodwin
IPC分类号： G03F1/00 , G03F1/74 , G03F9/00 , G23C14/00
CPC分类号： G03F1/74
摘要： Various methods of fabricating a reticle are provided. In one aspect, a pattern of opaque structures is formed on a plate capable of transmitting electromagnetic radiation. Adjacently positioned angled surfaces of the opaque structures are identified. Preselected portions of the opaque structures that encompass the adjacently positioned angled surfaces are then removed by ion-beam milling or other methods. Reticle patterns may be customized by modifying the structures of adjacent polygon structures that could otherwise give rise to diffraction-induced patterning errors on resist layers.
摘要翻译：提供制作掩模版的各种方法。一方面，在能够传输电磁辐射的板上形成不透明结构的图案。识别不透明结构的相邻定位的成角度的表面。然后通过离子束研磨或其它方法除去包围相邻定位的成角度表面的不透明结构的预选部分。标线图案可以通过修改相邻多边形结构的结构来定制，否则可能会在抗蚀剂层上引起衍射引起的图案化错误。

109. 发明授权

US6127251A Semiconductor device with a reduced width gate dielectric and method of making same 有权
标题翻译：具有减小宽度的栅极电介质的半导体器件及其制造方法
公开(公告)号：US6127251A
公开(公告)日：2000-10-03
申请号：US149398
申请日：1998-09-08
申请人： Mark I. Gardener , Frederick N. Hause , Charles E. May
发明人： Mark I. Gardener , Frederick N. Hause , Charles E. May
IPC分类号： H01L21/28 , H01L21/336 , H01L29/423 , H01L29/51 , H01L21/3205 , H01L21/4763
CPC分类号： H01L21/28185 , H01L21/28194 , H01L21/28202 , H01L29/42368 , H01L29/4991 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66575
摘要： The present invention is directed to a semiconductor device having a reduced feature size and a method of making same. The device is comprised of a gate dielectric positioned above a semiconducting substrate, and a gate conductor positioned above said gate dielectric. The width of the gate dielectric being less than the width of the gate conductor. The device further comprises a plurality of sidewall spacers adjacent said conductor. The method is comprised of forming a gate dielectric above the surface of a semiconducting substrate, forming a gate conductor above the gate dielectric, and wet etching the gate dielectric to a finished width that is less than the width of the gate conductor.
摘要翻译：本发明涉及具有减小的特征尺寸的半导体器件及其制造方法。该器件由位于半导体衬底上方的栅极电介质和位于栅极电介质上方的栅极导体构成。栅极电介质的宽度小于栅极导体的宽度。该装置还包括与所述导体相邻的多个侧壁间隔件。该方法包括在半导体衬底的表面上形成栅极电介质，在栅极电介质上方形成栅极导体，并将栅极电介质湿式蚀刻到小于栅极导体宽度的最终宽度。

110. 发明授权

US6114229A Polysilicon gate electrode critical dimension and drive current control in MOS transistor fabrication 有权
标题翻译：多晶硅栅极电极在MOS晶体管制造中的关键尺寸和驱动电流控制
公开(公告)号：US6114229A
公开(公告)日：2000-09-05
申请号：US196845
申请日：1998-11-20
申请人： Frederick N. Hause , Mark I. Gardner , Charles E. May
发明人： Frederick N. Hause , Mark I. Gardner , Charles E. May
IPC分类号： H01L21/28 , H01L21/20 , H01L21/3205 , H01L21/36 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/28035
摘要： A method is provided for controlling the critical dimensions of a polysilicon gate electrode, and for improving transistor drive current control. The method involves subjecting the gate structure of a transistor to a thermal treatment process in the presence of hydrogen gas. The thermal treatment process is performed subsequent to gate etching and photoresist mask removal, and provides gate electrodes having a more homogeneous linewidth, thereby improving transistor performance.
摘要翻译：提供了一种用于控制多晶硅栅电极的临界尺寸并提高晶体管驱动电流控制的方法。该方法包括在氢气存在下对晶体管的栅极结构进行热处理工艺。在栅极蚀刻和光致抗蚀剂掩模去除之后进行热处理工艺，并且提供具有更均匀的线宽的栅电极，从而提高晶体管性能。

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