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101. 发明授权

US06871258B2 METHOD FOR ERASING AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE, AND AN ELECTRICALLY ERASABLE NONVOLATILE MEMORY DEVICE, IN PARTICULAR AN EEPROM-FLASH MEMORY DEVICE 失效
标题翻译：用于擦除电可擦除非易失性存储器件的方法，特别是EEPROM闪速存储器件，以及特别是EEPROM闪速存储器件的电可擦除非易失性存储器件
公开(公告)号：US06871258B2
公开(公告)日：2005-03-22
申请号：US10159780
申请日：2002-05-30
申请人： Rino Micheloni , Giovanni Campardo , Salvatrice Scommegna
发明人： Rino Micheloni , Giovanni Campardo , Salvatrice Scommegna
IPC分类号： G11C16/34 , G06F12/00
CPC分类号： G11C16/344 , G11C16/3436
摘要： Described herein is an erase method for an electrically erasable nonvolatile memory device, in particular an EEPROM-FLASH nonvolatile memory device, comprising a memory array formed by a plurality of memory cells arranged in rows and columns and grouped in sectors each formed by a plurality of subsectors, which are in turn formed by one or more rows. Erase of the memory array is performed by sectors and for each sector envisages applying an erase pulse to the gate terminals of all the memory cells of the sector, verifying erase of the memory cells of each subsector, and applying a further erase pulse to the gate terminals of the memory cells of only the subsectors that are not completely erased.
摘要翻译：这里描述了一种用于电可擦除非易失性存储器件，特别是EEPROM闪存非易失性存储器件的擦除方法，其特征在于包括由排列成行和列的多个存储单元形成的存储器阵列，子行业，其又由一行或多行形成。存储器阵列的擦除由扇区执行，并且对于每个扇区，设想对扇区的所有存储器单元的栅极端子施加擦除脉冲，验证每个子部件的存储器单元的擦除，以及向栅极施加另外的擦除脉冲只有子部分的存储器单元的端子不被完全擦除。

102. 发明授权

US06809961B2 Regulation method for the drain, body and source terminals voltages in a non-volatile memory cell during a program phase and corresponding program circuit 有权
标题翻译：在程序阶段和对应的程序电路期间，非易失性存储单元中的漏极，体和源端子电压的调节方法
公开(公告)号：US06809961B2
公开(公告)日：2004-10-26
申请号：US10331116
申请日：2002-12-27
申请人： Rino Micheloni , Sabina Mognoni , Ilaria Motta , Andrea Sacco
发明人： Rino Micheloni , Sabina Mognoni , Ilaria Motta , Andrea Sacco
IPC分类号： G11C1604
CPC分类号： G11C16/30
摘要： A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.
摘要翻译：一种方法和程序加载电路用于调节正被编程的非易失性存储单元的漏极和体端子处的电压。这些电压从连接在导通图案中的编程负载电路施加，以将预定的电压值传送到存储单元的至少一个端子。该方法包括在编程负载电路内局部调节电压值以克服存在于导电图案中的寄生电阻的影响的步骤。

103. 发明授权

US06724658B2 Method and circuit for generating reference voltages for reading a multilevel memory cell 有权
标题翻译：用于产生用于读取多级存储单元的参考电压的方法和电路
公开(公告)号：US06724658B2
公开(公告)日：2004-04-20
申请号：US10133231
申请日：2002-04-26
申请人： Rino Micheloni , Giovanni Campardo
发明人： Rino Micheloni , Giovanni Campardo
IPC分类号： G11C1600
CPC分类号： G11C11/5621 , G11C5/147 , G11C7/067 , G11C11/56 , G11C11/5642 , G11C11/565 , G11C16/26 , G11C2211/5634
摘要： The circuit for generating reference voltages for reading a multilevel memory cell includes the following: a first memory cell and a second memory cell respectively having a first reference programming level and a second reference programming level; a first reference circuit and a second reference circuit respectively connected to said first and said second memory cells and having respective output terminals which respectively supply a first reference voltage and a second reference voltage; and a voltage divider having a first connection node and a second connection node respectively connected to the output terminals of the first reference circuit and of the second reference circuit to receive, respectively, the first reference voltage and the second reference voltage, and a plurality of intermediate nodes supplying respective third reference voltages at equal distances apart.
摘要翻译：用于产生用于读取多电平存储器单元的参考电压的电路包括：分别具有第一参考编程电平和第二参考编程电平的第一存储单元和第二存储单元; 分别连接到所述第一和所述第二存储单元的第一参考电路和第二参考电路，并具有分别提供第一参考电压和第二参考电压的相应输出端; 以及分压器，具有分别连接到第一参考电路和第二参考电路的输出端的第一连接节点和第二连接节点，以分别接收第一参考电压和第二参考电压，以及多个中间节点以相等的距离提供相应的第三参考电压。

104. 发明授权

US06642776B1 Bandgap voltage reference circuit 有权
标题翻译：带隙电压参考电路
公开(公告)号：US06642776B1
公开(公告)日：2003-11-04
申请号：US09541577
申请日：2000-04-03
申请人： Rino Micheloni , Luca Crippa
发明人： Rino Micheloni , Luca Crippa
IPC分类号： G05F110
CPC分类号： G05F3/30
摘要： Bandgap voltage reference circuit with an output voltage that remains stable in the range of a temperature of utilization. The circuit includes a first circuit block, a second circuit block, and a control circuit connected with said circuit blocks, said first circuit block including a bandgap circuit with a low power consumption, said second circuit block including a bandgap circuit with a short start up time, said control circuit suitable to control said two circuit blocks in a such way that said output voltage of said bandgap voltage reference circuit is supplied by said second circuit block at the starting of said first circuit block for a period of time and said output voltage is supplied by said first circuit block for the period of time subsequent to said period of time and that lasts until the turning off of the circuit, said second circuit block being turned off after said period of time.
摘要翻译：带隙电压参考电路，输出电压在使用温度范围内保持稳定。电路包括第一电路块，第二电路块和与所述电路块连接的控制电路，所述第一电路块包括具有低功耗的带隙电路，所述第二电路块包括具有短启动的带隙电路所述控制电路适于以这样的方式控制所述两个电路块，使得所述带隙电压参考电路的所述输出电压在所述第一电路块的启动期间由所述第二电路块提供一段时间，并且所述输出电压由所述第一电路块供给所述时间段之后的时间段，并持续到所述电路的断开，所述第二电路块在所述时间段之后被关断。

105. 发明授权

US06603681B2 Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method 有权
公开(公告)号：US06603681B2
公开(公告)日：2003-08-05
申请号：US10002599
申请日：2001-10-31
申请人： Rino Micheloni , Andrea Sacco
发明人： Rino Micheloni , Andrea Sacco
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/10
摘要： A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

106. 发明授权

US06542404B2 Small size, low consumption, multilevel nonvolatile memory 有权
标题翻译：小尺寸，低功耗，多级非易失性存储器
公开(公告)号：US06542404B2
公开(公告)日：2003-04-01
申请号：US09972726
申请日：2001-10-04
申请人： Andrea Pierin , Stefano Gregori , Rino Micheloni , Osama Khouri , Guido Torelli
发明人： Andrea Pierin , Stefano Gregori , Rino Micheloni , Osama Khouri , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C16/30 , G11C5/145 , G11C7/06 , G11C11/5621 , G11C11/5642 , G11C16/26
摘要： A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).
摘要翻译：多级非易失性存储器包括提供电源电压（VDD）的电源线（28），提供高于电源电压（VDD）的升压电压（Vp）的升压电路（26），连接的升压线路到升压电路（26）和包括至少一个比较器（35）的读取电路（25）。比较器（35）包括第一和第二输入（35a，35b），第一和第二输出（45a，45b），连接到升压线（30）的至少一个放大级（40）线路锁存级（41）连接到电源线（28）。

107. 发明授权

US06532171B2 Nonvolatile semiconductor memory capable of selectively erasing a plurality of elemental memory units 有权
标题翻译：能够选择性地擦除多个元件存储器单元的非易失性半导体存储器
公开(公告)号：US06532171B2
公开(公告)日：2003-03-11
申请号：US09919789
申请日：2001-07-31
申请人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
发明人： Roberto Gastaldi , Paolo Cappelletti , Giulio Casagrande , Giovanni Campardo , Rino Micheloni
IPC分类号： G11C1616
CPC分类号： G11C16/3431 , G11C16/16 , G11C16/34
摘要： A semiconductor memory such as a flash memory, which comprises at least one two-dimensional array of memory cells with a plurality of rows and columns of memory cells grouped in a plurality of packets. The memory cells belonging to the columns of each packet are formed in a respective semiconductor region with a first type of conductivity, this region being distinct from the semiconductor regions with the first type of conductivity in which the memory cells belonging to the columns of the remaining packets are formed. The semiconductor regions with the first type of conductivity divide the set of memory cells belonging to each row into a plurality of subsets of memory cells that constitute elemental memory units which can be modified individually. Thus memory units of very small dimensions can be erased individually, without excessive overhead in terms of area.
摘要翻译：诸如闪速存储器的半导体存储器，其包括具有分组在多个分组中的多个存储单元的行和列的存储器单元的至少一个二维阵列。属于每个分组的列的存储单元形成在具有第一类型导电性的相应半导体区域中，该区域与具有第一类型导电性的半导体区域不同，其中存储单元属于剩余的列形成包。具有第一类型导电性的半导体区域将属于每一行的存储单元集合分成多个存储单元子集，这些存储单元子集构成可单独修改的元素存储单元。因此，可以单独擦除非常小尺寸的存储单元，而在面积方面没有过多的开销。

108. 发明授权

US06504758B2 Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding 有权
公开(公告)号：US06504758B2
公开(公告)日：2003-01-07
申请号：US09960851
申请日：2001-09-21
申请人： Andrea Sacco , Osama Khouri , Rino Micheloni , Guido Torelli
发明人： Andrea Sacco , Osama Khouri , Rino Micheloni , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C5/147 , G11C8/08 , G11C8/10 , G11C8/14
摘要： Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

109. 发明授权

US06424121B1 Voltage generator switching between alternating, first and second voltage values, in particular for programming multilevel cells 有权
标题翻译：电压发生器在交替，第一和第二电压值之间切换，特别是用于编程多电平单元
公开(公告)号：US06424121B1
公开(公告)日：2002-07-23
申请号：US09714837
申请日：2000-11-15
申请人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
IPC分类号： H01M1046
CPC分类号： G11C11/56 , G11C16/30
摘要： A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.
摘要翻译：由充电电路和具有可变电阻的公共可编程分压器的放电电路构成的电压发生器; 所述可编程分压器包括串联布置并且可选择地连接的多个电阻器，以可选地定义逐步增加的编程电压和固定验证电压。所述充电电路由电压调节器形成，所述稳压器在输出端提供由所述可编程分压器确定的精确电压值，以及当所述输出电压必须以受控方式从较高值切换到较低值时插入所述放电电路。

110. 发明授权

US06356481B1 Row decoder for a nonvolatile memory with capability of selectively biasing word lines to positive or negative voltages 失效
标题翻译：用于非易失性存储器的行解码器，其具有将字线选择性地偏置为正或负电压的能力
公开(公告)号：US06356481B1
公开(公告)日：2002-03-12
申请号：US09595054
申请日：2000-06-16
申请人： Rino Micheloni , Giovanni Campardo , Atsushi Ohba , Marcello Carrera
发明人： Rino Micheloni , Giovanni Campardo , Atsushi Ohba , Marcello Carrera
IPC分类号： G11C1606
CPC分类号： G11C11/5621 , G11C8/08 , G11C8/14 , G11C16/08 , G11C16/12 , G11C16/30
摘要： The row decoder includes, for each word line of the memory, a respective biasing circuit receiving at the input a row selection signal switching, in preset operating conditions, between a supply voltage and a ground voltage and supplying at the output a biasing signal for the respective word line switching between a first operating voltage, in turn switching at least between the supply voltage and a programming voltage higher than the supply voltage, and a second operating voltage, in turn switching at least between the ground voltage and an erase voltage lower than the ground voltage. Each biasing circuit includes a level translator circuit receiving at the input the row selection signal and supplying as output a control signal switching between the first and the second operating voltages and an output driver circuit receiving as input the control signal and supplying at the output the biasing signal.
摘要翻译：行解码器包括对于存储器的每个字线，相应的偏置电路在输入端接收行选择信号，在预设工作条件下，在电源电压和接地电压之间切换，并在输出端提供偏置信号，相应的字线在第一工作电压之间切换，进而至少在电源电压和高于电源电压的编程电压之间切换，以及第二工作电压，进而至少在接地电压和擦除电压之间切换接地电压。每个偏置电路包括电平转换器电路，其在输入处接收行选择信号，并且作为输出提供在第一和第二操作电压之间切换的控制信号;以及输出驱动器电路，作为输入接收控制信号，并在输出端提供偏置信号。

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