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1. 发明授权

US06456150B1 Circuit for biasing a bulk terminal of a MOS transistor 有权
标题翻译：用于偏置MOS晶体管的体积端子的电路
公开(公告)号：US06456150B1
公开(公告)日：2002-09-24
申请号：US09661601
申请日：2000-09-14
申请人： Andrea Sacco , Rino Micheloni , Marco Scotti
发明人： Andrea Sacco , Rino Micheloni , Marco Scotti
IPC分类号： H03K301
CPC分类号： H03K19/00315
摘要： A circuit for biasing the bulk terminal of a first MOS transistor having a first terminal connected to a first line set to a first potential, and a second terminal connected to a second line set to a second potential. The biasing circuit includes a second and a third MOS transistors having first terminals connected respectively to the first line and to the second line, second terminals connected to the bulk terminal of the first MOS transistor, and control terminals connected respectively to the second and to the first line.
摘要翻译：一种用于偏置第一MOS晶体管的体积端子的电路，其具有连接到设置为第一电位的第一线路的第一端子，以及连接到设置为第二电位的第二线路的第二端子。偏置电路包括第二和第三MOS晶体管，其具有分别连接到第一线路和第二线路的第一端子，连接到第一MOS晶体管的体积端子的第二端子和分别连接到第二线路和第二端子的控制端子第一行。

2. 发明授权

US06259632B1 Capacitive compensation circuit for the regulation of the word line reading voltage in non-volatile memories 有权
标题翻译：用于调节非易失性存储器中字线读取电压的电容补偿电路
公开(公告)号：US06259632B1
公开(公告)日：2001-07-10
申请号：US09491475
申请日：2000-01-19
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
IPC分类号： G11C1606
CPC分类号： G11C11/5621 , G11C8/14 , G11C16/08 , G11C16/30
摘要： Circuit for the regulation of the word line voltage in a memory, including a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when said one or more word lines are being selected, and charge accumulation means that are selectively connectable with the output of the voltage regulator and suitable to accumulate a compensation charge for a voltage drop that takes place on said regulated voltage upon the selection of said one or more word lines of the memory.
摘要翻译：用于调节存储器中的字线电压的电路，包括适于在选择所述一个或多个字线时产生要提供给存储器的一个或多个字线的输出调节电压的电压调节器，以及电荷累积意味着可以选择性地与电压调节器的输出端连接，并且适合于在选择存储器的所述一个或多个字线时，对在所述调节电压上发生的电压降累积补偿电荷。

3. 发明授权

US06809961B2 Regulation method for the drain, body and source terminals voltages in a non-volatile memory cell during a program phase and corresponding program circuit 有权
标题翻译：在程序阶段和对应的程序电路期间，非易失性存储单元中的漏极，体和源端子电压的调节方法
公开(公告)号：US06809961B2
公开(公告)日：2004-10-26
申请号：US10331116
申请日：2002-12-27
申请人： Rino Micheloni , Sabina Mognoni , Ilaria Motta , Andrea Sacco
发明人： Rino Micheloni , Sabina Mognoni , Ilaria Motta , Andrea Sacco
IPC分类号： G11C1604
CPC分类号： G11C16/30
摘要： A method and program-load circuit is for regulating the voltages at the drain and body terminals of a non-volatile memory cell being programmed. These voltages are applied from a program-load circuit connected in a conduction pattern to transfer a predetermined voltage value to at least one terminal of the memory cell. The method includes a step of regulating the voltage value locally, within the program-load circuit, to overcome the effect of a parasitic resistor present in the conduction pattern.
摘要翻译：一种方法和程序加载电路用于调节正被编程的非易失性存储单元的漏极和体端子处的电压。这些电压从连接在导通图案中的编程负载电路施加，以将预定的电压值传送到存储单元的至少一个端子。该方法包括在编程负载电路内局部调节电压值以克服存在于导电图案中的寄生电阻的影响的步骤。

4. 发明授权

US06603681B2 Method of pulse programming, in particular for high-parallelism memory devices, and a memory device implementing the method 有权
公开(公告)号：US06603681B2
公开(公告)日：2003-08-05
申请号：US10002599
申请日：2001-10-31
申请人： Rino Micheloni , Andrea Sacco
发明人： Rino Micheloni , Andrea Sacco
IPC分类号： G11C1604
CPC分类号： G11C16/24 , G11C16/10
摘要： A pulse programming method for a non-volatile memory device includes: addressing memory cells to be programmed within the device by selecting corresponding hierarchic decoder transistors; biasing the gate terminals of the memory cells; and programming the memory cells by applying a voltage pulse, regulated by a bias circuit, to the drain terminals of the memory cells. Advantageously, the programming method further comprises a step of precharging an internal node of the bias circuit before starting the programming step, the internal node being connected to a parasitic capacitance of the memory device.

5. 发明授权

US06504758B2 Control circuit for a variable-voltage regulator of a nonvolatile memory with hierarchical row decoding 有权
公开(公告)号：US06504758B2
公开(公告)日：2003-01-07
申请号：US09960851
申请日：2001-09-21
申请人： Andrea Sacco , Osama Khouri , Rino Micheloni , Guido Torelli
发明人： Andrea Sacco , Osama Khouri , Rino Micheloni , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C5/147 , G11C8/08 , G11C8/10 , G11C8/14
摘要： Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.

6. 发明授权

US06424121B1 Voltage generator switching between alternating, first and second voltage values, in particular for programming multilevel cells 有权
标题翻译：电压发生器在交替，第一和第二电压值之间切换，特别是用于编程多电平单元
公开(公告)号：US06424121B1
公开(公告)日：2002-07-23
申请号：US09714837
申请日：2000-11-15
申请人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
IPC分类号： H01M1046
CPC分类号： G11C11/56 , G11C16/30
摘要： A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.
摘要翻译：由充电电路和具有可变电阻的公共可编程分压器的放电电路构成的电压发生器; 所述可编程分压器包括串联布置并且可选择地连接的多个电阻器，以可选地定义逐步增加的编程电压和固定验证电压。所述充电电路由电压调节器形成，所述稳压器在输出端提供由所述可编程分压器确定的精确电压值，以及当所述输出电压必须以受控方式从较高值切换到较低值时插入所述放电电路。

7. 发明授权

US06307778B1 Non volatile memory with detection of short circuits between word lines 失效
标题翻译：非易失性存储器，检测字线之间的短路
公开(公告)号：US06307778B1
公开(公告)日：2001-10-23
申请号：US09658236
申请日：2000-09-08
申请人： Rino Micheloni , Andrea Sacco , Sabina Mognoni
发明人： Rino Micheloni , Andrea Sacco , Sabina Mognoni
IPC分类号： G11C1606
CPC分类号： G11C29/50 , G01R31/3004 , G11C29/02
摘要： The non volatile memory device integrates, in one and the same chip, the array of memory cells, a voltage regulator which supplies a regulated operating voltage to a selected word line, and a short circuit detecting circuit. The short circuit detecting circuit detects the output voltage of the voltage regulator, which is correlated to the current for biasing the cells of the word line selected. Once settled to the steady state condition, the output current assumes one first value in the absence of short circuits, and one second value in the presence of a short circuit between the word line selected and one or more adjacent word lines. The short circuit detecting circuit compares the output current of the voltage regulator with a reference value and generates at output a short circuit digital signal which indicates the presence or otherwise of a short circuit.
摘要翻译：非易失性存储器件在同一芯片中集成了存储单元阵列，向所选字线提供调节工作电压的电压调节器和短路检测电路。短路检测电路检测电压调节器的输出电压，其与用于偏置所选字线的单元的电流相关。一旦稳定到稳定状态，输出电流在没有短路的情况下呈现一个第一值，并且在所选择的字线和一个或多个相邻字线之间存在短路的情况下，存在一个第二值。短路检测电路将电压调节器的输出电流与参考值进行比较，并在输出端产生指示短路的存在或短路的短路数字信号。

8. 发明授权

US06259635B1 Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories 有权
标题翻译：用于调节非易失性存储器中字线读取电压的电容式升压电路
公开(公告)号：US06259635B1
公开(公告)日：2001-07-10
申请号：US09491476
申请日：2000-01-19
申请人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Ilaria Motta , Andrea Sacco , Guido Torelli
IPC分类号： G11C1604
CPC分类号： G11C16/26 , G11C5/145 , G11C8/08 , G11C8/14 , G11C11/5621 , G11C11/5642 , G11C16/08 , G11C16/30
摘要： A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.
摘要翻译：一种用于调节存储器中的字线电压的电路，包括适于在选择一个或多个字线时产生要提供给存储器的一个或多个字线的输出调节电压的电压调节器。该电路包括一个升压电路，其耦合到所述电压调节器的输出端，并且可以在选择一个或多个存储器字线时被激活，以便在选择一个或多个存储器字线时升高调节电压。

9. 发明授权

US06650173B1 Programmable voltage generator 有权
标题翻译：可编程电压发生器
公开(公告)号：US06650173B1
公开(公告)日：2003-11-18
申请号：US09714852
申请日：2000-11-15
申请人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
发明人： Osama Khouri , Rino Micheloni , Andrea Sacco , Guido Torelli
IPC分类号： G05F110
CPC分类号： G11C29/021 , G11C5/147 , G11C11/56 , G11C16/30 , G11C29/028 , G11C2029/5004
摘要： The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.
摘要翻译：电压发生器包括负反馈回路，其包括具有反馈节点的可编程分压器。分压器包括设置在电压发生器的输出端和反馈节点之间并具有可变电阻的可编程电阻器。可编程电阻器包括固定电阻器和彼此串联布置并且限定多个中间节点的多个附加电阻器。附加电阻器可以通过设置在电压发生器的输出端和各个中间节点之间的开关选择性地连接，以便根据提供给开关的命令信号来定义可编程的输出电压V0。

10. 发明授权

US06373780B1 Single supply voltage nonvolatile memory device with row decoding 有权
标题翻译：单电源电压非易失性存储器件，具有行解码功能
公开(公告)号：US06373780B1
公开(公告)日：2002-04-16
申请号：US09627273
申请日：2000-07-28
申请人： Rino Micheloni , Osama Khouri , Andrea Sacco , Massimiliano Picca
发明人： Rino Micheloni , Osama Khouri , Andrea Sacco , Massimiliano Picca
IPC分类号： G11C800
CPC分类号： G11C5/145 , G11C5/14 , G11C8/10
摘要： The memory device comprises a memory array having an organization of the type comprising global word lines and local word lines, a global row decoder addressing the global word lines, a local row decoder addressing the local word lines, a global power supply stage supplying the global row decoder, and a local power supply stage supplying the local row decoder.
摘要翻译：存储器件包括具有包括全局字线和本地字线的组织的存储器阵列，寻址全局字线的全局行解码器，寻址本地字线的本地行解码器，提供全局字线的全局电源级行解码器，以及供应本地行解码器的本地电源级。

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