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101. 发明授权

US06990009B2 Nanotube-based switching elements with multiple controls 失效
标题翻译：基于纳米管的开关元件具有多个控制
公开(公告)号：US06990009B2
公开(公告)日：2006-01-24
申请号：US10918085
申请日：2004-08-13
申请人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal
发明人： Claude L. Bertin , Thomas Rueckes , Brent M. Segal
IPC分类号： G11C11/00
CPC分类号： H01L29/0665 , B82Y10/00 , G11C13/025 , G11C23/00 , G11C2213/17 , H01H1/0094 , H01H1/027 , H01L27/28 , H01L29/0673 , H01L29/73 , H01L29/78 , H01L51/0048 , H01L51/0508 , Y10S977/708 , Y10S977/932 , Y10S977/936 , Y10S977/938 , Y10S977/94 , Y10S977/943
摘要： Nanotube-based switching elements with multiple controls and circuits made from such. A switching element includes an input node, an output node, and a nanotube channel element having at least one electrically conductive nanotube. A control structure is disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The output node is constructed and arranged so that channel formation is substantially unaffected by the electrical state of the output node. The control structure includes a control electrode and a release electrode, disposed on opposite sides of the nanotube channel element. The control and release may be used to form a differential input, or if the device is constructed appropriately to operate the circuit in a non-volatile manner. The switching elements may be arranged into logic circuits and latches having differential inputs and/or non-volatile behavior depending on the construction.
摘要翻译：基于纳米管的开关元件具有由此制成的多个控制和电路。开关元件包括输入节点，输出节点和具有至少一个导电纳米管的纳米管通道元件。相对于纳米管通道元件设置控制结构，以可控地形成和取消所述输入节点和所述输出节点之间的导电通道。输出节点的构造和布置使得通道形成基本上不受输出节点的电气状态的影响。控制结构包括设置在纳米管通道元件的相对侧上的控制电极和释放电极。控制和释放可用于形成差分输入，或者如果该装置被适当地构造以以非易失性方式操作电路。根据结构，开关元件可以被布置成具有差分输入和/或非易失性行为的逻辑电路和锁存器。

102. 发明授权

US09362390B2 Logic elements comprising carbon nanotube field effect transistor (CNTFET) devices and methods of making same 有权
标题翻译：包括碳纳米管场效应晶体管（CNTFET）器件的逻辑元件及其制造方法
公开(公告)号：US09362390B2
公开(公告)日：2016-06-07
申请号：US13579828
申请日：2011-02-22
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H01L29/78 , B82Y10/00 , H01L51/00 , H03K19/20 , H01L21/02 , H01L29/16 , H01L27/28 , H01L51/05 , B82Y40/00
CPC分类号： H01L27/283 , B82Y10/00 , B82Y40/00 , G06F17/5045 , H01L21/02376 , H01L29/16 , H01L29/78 , H01L51/0048 , H01L51/0558 , H01L51/0566 , H01L51/105 , H03K19/20 , Y10S977/742
摘要： Inverter circuits and NAND circuits comprising nanotube based FETs and methods of making the same are described. Such circuits can be fabricating using field effect transistors comprising a source, a drain, a channel region, and a gate, wherein the first channel region includes a fabric of semiconducting nanotubes of a given conductivity type. Such FETs can be arranged to provide inverter circuits in either two-dimension or three-dimensional (stacked) layouts. Design equations based upon consideration of the electrical characteristics of the nanotubes are described which permit optimization of circuit design layout based upon constants that are indicative of the current carrying capacity of the nanotube fabrics of different FETs.
摘要翻译：描述了包括基于纳米管的FET的逆变器电路和NAND电路及其制造方法。这样的电路可以使用包括源极，漏极，沟道区和栅极的场效应晶体管来制造，其中第一沟道区包括具有给定导电类型的半导体纳米管的织物。这样的FET可以被布置成以二维或三维（堆叠）布局提供逆变器电路。描述了基于对纳米管的电特性的考虑的设计方程，其基于指示不同FET的纳米管织物的载流能力的常数来优化电路设计布局。

103. 发明授权

US07906991B2 Nanotube-based logic driver circuits 失效
标题翻译：基于纳米管的逻辑驱动电路
公开(公告)号：US07906991B2
公开(公告)日：2011-03-15
申请号：US11897812
申请日：2007-08-31
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H03K19/20
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/16 , H03K19/02
摘要： Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.
摘要翻译：基于纳米管的逻辑驱动电路。这些包括上拉驱动电路，推挽驱动电路，三态驱动电路等。在一个实施例中，片外驱动器电路包括具有第一和第二信号链路的差分输入，每个信号链路耦合到两个差分片上信号中的相应一个。至少一个输出链路可连接到片外阻抗负载，并且至少一个开关元件具有输入节点，输出节点，纳米管通道元件和相对于纳米管通道元件设置的可控制地形成的控制结构并且在所述输入节点和所述输出节点之间取消导电通道。输入节点耦合到参考信号，并且控制结构耦合到第一和第二信号链路。输出节点耦合到输出链路，并且信道单元的大小适于承载足够的电流以驱动所述片外阻抗负载。

104. 发明授权

US07859311B2 Integrated nanotube and field effect switching devices 有权
标题翻译：集成纳米管和场效应开关器件
公开(公告)号：US07859311B2
公开(公告)日：2010-12-28
申请号：US12506525
申请日：2009-07-21
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H03K19/094
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/17 , H01H1/0094 , H03K17/545 , H03K19/08 , Y10S977/70 , Y10S977/94
摘要： Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.
摘要翻译：混合开关器件将纳米管开关元件与诸如NFET和PFET之类的场效应器件集成。开关装置根据控制输入的相对状态，将导电通道从输入到输出的信号输入形成和取消。在本发明的实施例中，导电通道包括纳米管通道元件和场可调制半导体通道元件。开关装置可以包括串联电配置的纳米管开关元件和场效应器件。根据本发明的一个方面，集成开关装置是具有信号输入端子，控制输入端子，第二输入端子和输出端子的四端子装置。这些设备可能是非易失性的。这些器件可以构成混合型NT-FET逻辑系列的基础，可用于实现任何布尔逻辑电路。

105. 发明申请

US20100267205A1 CARBON NANOTUBES FOR THE SELECTIVE TRANSFER OF HEAT FROM ELECTRONICS 有权
标题翻译：碳纳米管用于电子选择性转移
公开(公告)号：US20100267205A1
公开(公告)日：2010-10-21
申请号：US12066063
申请日：2006-09-05
申请人： Jonathan W. Ward , Claude L. Bertin , Brent M. Segal
发明人： Jonathan W. Ward , Claude L. Bertin , Brent M. Segal
IPC分类号： H01L23/373 , H01L21/70 , H01L21/02
CPC分类号： H01L23/373 , H01L23/433 , H01L24/28 , H01L24/31 , H01L2224/0554 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/73253 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01019 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/14 , Y10S977/80 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Under one aspect, a method of cooling a circuit element includes providing a thermal reservoir having a temperature lower than an operating temperature of the circuit element; and providing a nanotube article in thermal contact with the circuit element and with the reservoir, the nanotube article including a non-woven fabric of nanotubes in contact with other nanotubes to define a plurality of thermal pathways along the article, the nanotube article having a nanotube density and a shape selected such that the nanotube article is capable of transferring heat from the circuit element to the thermal reservoir.
摘要翻译：在一个方面，冷却电路元件的方法包括提供具有低于电路元件的工作温度的温度的热存储器; 并且提供与所述电路元件和所述储存器热接触的纳米管制品，所述纳米管制品包括与其它纳米管接触的纳米管的无纺织物以限定沿着所述制品的多个热路径，所述纳米管制品具有纳米管密度和形状，使得纳米管制品能够将热量从电路元件传递到热储存器。

106. 发明申请

US20100079165A1 NONVOLATILE NANOTUBE PROGRAMMABLE LOGIC DEVICES AND A NONVOLATILE NANOTUBE FIELD PROGRAMMABLE GATE ARRAY USING SAME 有权
公开(公告)号：US20100079165A1
公开(公告)日：2010-04-01
申请号：US12536752
申请日：2009-08-06
申请人： Claude L. Bertin , Brent M. Segal
发明人： Claude L. Bertin , Brent M. Segal
IPC分类号： H03K19/094 , H03K17/687 , H03K19/0175
CPC分类号： G11C13/0069 , B82Y10/00 , G11C13/0004 , G11C13/0007 , G11C13/004 , G11C13/0061 , G11C13/025 , G11C23/00 , G11C29/02 , G11C29/021 , G11C29/023 , G11C29/028 , G11C2013/0042 , G11C2013/0054 , G11C2213/35 , G11C2213/82 , H03K19/17728 , H03K19/17736 , H03K19/1776 , H03K19/1778 , H03K19/17796 , Y10S977/94
摘要： Field programmable device (FPD) chips with large logic capacity and field programmability that are in-circuit programmable are described. FPDs use small versatile nonvolatile nanotube switches that enable efficient architectures for dense low power and high performance chip implementations and are compatible with low cost CMOS technologies and simple to integrate.

107. 发明授权

US07564269B2 Integrated nanotube and field effect switching devices 有权
标题翻译：集成纳米管和场效应开关器件
公开(公告)号：US07564269B2
公开(公告)日：2009-07-21
申请号：US11929076
申请日：2007-10-30
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H03K19/094
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/17 , H01H1/0094 , H03K17/545 , H03K19/08 , Y10S977/70 , Y10S977/94
摘要： Hybrid switching devices integrate nanotube switching elements with field effect devices, such as NFETs and PFETs. A switching device forms and unforms a conductive channel from the signal input to the output subject to the relative state of the control input. In embodiments of the invention, the conductive channel includes a nanotube channel element and a field modulatable semiconductor channel element. The switching device may include a nanotube switching element and a field effect device electrically disposed in series. According to one aspect of the invention, an integrated switching device is a four-terminal device with a signal input terminal, a control input terminal, a second input terminal, and an output terminal. The devices may be non-volatile. The devices can form the basis for a hybrid NT-FET logic family and can be used to implement any Boolean logic circuit.
摘要翻译：混合开关器件将纳米管开关元件与场效应器件（例如NFET和PFET）集成。开关装置根据控制输入的相对状态，将导电通道从输入到输出的信号输入形成和取消。在本发明的实施例中，导电通道包括纳米管通道元件和场可调制半导体通道元件。开关装置可以包括串联电配置的纳米管开关元件和场效应器件。根据本发明的一个方面，集成开关器件是具有信号输入端子，控制输入端子，第二输入端子和输出端子的四端子器件。这些设备可能是非易失性的。这些器件可以构成混合型NT-FET逻辑系列的基础，可用于实现任何布尔逻辑电路。

108. 发明授权

US07265575B2 Nanotube-based logic driver circuits 有权
公开(公告)号：US07265575B2
公开(公告)日：2007-09-04
申请号：US11653673
申请日：2007-01-16
申请人： Claude L. Bertin
发明人： Claude L. Bertin
IPC分类号： H03K19/003 , H03K19/23
CPC分类号： G11C13/025 , B82Y10/00 , G11C23/00 , G11C2213/16 , H03K19/02
摘要： Nanotube based logic driver circuits. These include pull-up driver circuits, push-pull driver circuits, tristate driver circuits, among others. Under one embodiment, an off-chip driver circuit includes a differential input having first and second signal links, each coupled to a respective one of two differential, on-chip signals. At least one output link is connectable to an off-chip impedance load, and at least one switching element has an input node, an output node, a nanotube channel element, and a control structure disposed in relation to the nanotube channel element to controllably form and unform an electrically conductive channel between said input node and said output node. The input node is coupled to a reference signal and the control structure is coupled to the first and second signal links. The output node is coupled to the output link, and the channel element is sized to carry sufficient current to drive said off-chip impedance load.

109. 发明授权

US06802033B1 Low-power critical error rate communications controller 失效
标题翻译：低功率关键错误率通信控制器
公开(公告)号：US06802033B1
公开(公告)日：2004-10-05
申请号：US09286855
申请日：1999-04-06
申请人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
发明人： Claude L. Bertin , Alvar A. Dean , Kenneth J. Goodnow , Scott W. Gould , Patrick E. Perry , Wilbur D. Pricer , William R. Tonti
IPC分类号： G06F1100
CPC分类号： G06F11/10 , H04L1/0053
摘要： A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.
摘要翻译：一种在通信控制器上动态修改错误恢复的方式，以在当前错误率条件允许的最低功耗模式下工作。当操作条件良好并且检测到少量错误时，输入低功率错误检测/校正模式，从而节省电池寿命。低功率误差校正机构运行频率较低，功率低于大功率机构，并为控制器保持相同的数据速率，从而节省功耗。选择控制器错误（电源）模式可以是外部的，例如当语音数据太嘈杂时，人们在蜂窝电话上使用控制拨盘。或者，选择可以是自动的，在内部进行选择的关键误差电平检测器。

110. 发明授权

US06518112B2 High performance, low power vertical integrated CMOS devices 失效
公开(公告)号：US06518112B2
公开(公告)日：2003-02-11
申请号：US09899262
申请日：2001-07-06
申请人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
发明人： Michael D. Armacost , Claude L. Bertin , Erik L. Hedberg , Jack A. Mandelman
IPC分类号： H01L31119
CPC分类号： H01L27/11 , H01L21/823885 , H01L21/84 , H01L27/1104 , H01L27/1203 , Y10S257/903
摘要： A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETs; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device's channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.

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