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101. 发明授权

US07065665B2 Interlocked synchronous pipeline clock gating 有权
公开(公告)号：US07065665B2
公开(公告)日：2006-06-20
申请号：US10262769
申请日：2002-10-02
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： H04L5/00 , G06F9/30
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.

102. 发明申请

US20100083203A1 Modeling System-Level Effects of Soft Errors 有权
标题翻译：软错误的系统级效应建模
公开(公告)号：US20100083203A1
公开(公告)日：2010-04-01
申请号：US12243427
申请日：2008-10-01
申请人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
发明人： Pradip Bose , Prabhakar N. Kudva , Jude A. Rivers , Pia N. Sanda , John-David Wellman
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F2217/82
摘要： Mechanisms for modeling system level effects of soft errors are provided. Mechanisms are provided for integrating device-level and component-level soft error rate (SER) analysis mechanisms with micro-architecture level performance analysis tools during a concept phase of the IC design to thereby generate a SER analysis tool. A first SER profile for the IC design is generated by applying the SER analysis tool to the IC design. At a later phase of the IC design, detailed information about SER vulnerabilities of logic and storage elements within the IC design are obtained and the first SER profile is refined based on the detailed information about SER vulnerabilities to thereby generate a second SER profile for the IC design. Modifications to the IC design are made at one or more phases of the IC design based on one of the first SER profile or the second SER profile.
摘要翻译：提供了对软错误的系统级别影响进行建模的机制。提供了在IC设计的概念阶段将器件级和组件级软错误率（SER）分析机制与微架构级性能分析工具集成的机制，从而生成SER分析工具。通过将SER分析工具应用于IC设计，可以生成IC设计的第一个SER简档。在IC设计的后期阶段，获得关于IC设计中逻辑和存储元件的SER漏洞的详细信息，并且基于关于SER漏洞的详细信息来改进第一SER简档，从而为IC生成第二SER简档设计。基于第一SER简档或第二SER简档中的一个，在IC设计的一个或多个阶段进行对IC设计的修改。

103. 发明授权

US07454316B2 Method and apparatus for monitoring and enhancing on-chip microprocessor reliability 有权
标题翻译：用于监控和增强片上微处理器可靠性的方法和装置
公开(公告)号：US07454316B2
公开(公告)日：2008-11-18
申请号：US10961613
申请日：2004-10-08
申请人： Pradip Bose , Jude A. Rivers , Jayanth Srinivasan
发明人： Pradip Bose , Jude A. Rivers , Jayanth Srinivasan
IPC分类号： G06F11/30 , G21C17/00
CPC分类号： G06F11/008
摘要： A system and method for projecting reliability to manage system functions includes an activity module which determines activity in the system. A reliability module interacts with the activity module to determine a reliability measurement for the module in real-time based upon the activity and measured operational quantities of the system. A management module manages actions of the system based upon the reliability measurement input from the reliability module. This may be to provide corrective action, to reallocate resources, increase reliability of the module, etc.
摘要翻译：用于投影可靠性以管理系统功能的系统和方法包括确定系统中的活动的活动模块。可靠性模块与活动模块进行交互，以基于系统的活动和测量的运行量实时地确定模块的可靠性测量。管理模块基于来自可靠性模块的可靠性测量输入来管理系统的动作。这可能是提供纠正措施，重新分配资源，增加模块的可靠性等。

104. 发明申请

US20080229134A1 RELIABILITY MORPH FOR A DUAL-CORE TRANSACTION-PROCESSING SYSTEM 审中-公开
标题翻译：双核交易处理系统的可靠性模型
公开(公告)号：US20080229134A1
公开(公告)日：2008-09-18
申请号：US11684987
申请日：2007-03-12
申请人： Pradip Bose , Philip George Emma , Jude A. Rivers , Sumedh Wasudeo Sathaye
发明人： Pradip Bose , Philip George Emma , Jude A. Rivers , Sumedh Wasudeo Sathaye
IPC分类号： G06F15/76
CPC分类号： G06F9/3836 , G06F9/30189 , G06F9/3851 , G06F9/3855 , G06F9/3863 , G06F9/3885
摘要： In processors having buffers to manage instruction flow referred to as a ReOrder Buffer (ROB) it is shown that these buffers are of the same approximate size of a checkpoint array for architected state. In a particular “morphing mode” in which a pair of processors can be configured to provide different functionalities on demand, a new “High-Reliability” (HR) mode is provided in which the ROB of one of the processors is used for a checkpoint array, and the pair of processors is made to run in lockstep on a single instruction stream under the control of the remaining ROB so as to provide redundant, hence highly-reliable computing.
摘要翻译：在具有用于管理称为ReOrder缓冲器（ROB）的指令流的缓冲器的处理器中，示出了这些缓冲器具有与用于架构状态的检查点阵列相同的近似大小。在一种特定的“变形模式”中，其中一对处理器可以被配置为按需提供不同的功能，提供了一种新的“高可靠性”（HR）模式，其中一个处理器的ROB用于检查点阵列，并且使一对处理器在剩下的ROB的控制下在单个指令流上锁定运行，以提供冗余的，因此高度可靠的计算。

105. 发明申请

US20060080062A1 Method and apparatus for monitoring and enhancing on-chip microprocessor reliability 有权
标题翻译：用于监控和增强片上微处理器可靠性的方法和装置
公开(公告)号：US20060080062A1
公开(公告)日：2006-04-13
申请号：US10961613
申请日：2004-10-08
申请人： Pradip Bose , Jude Rivers , Jayanth Srinivasan
发明人： Pradip Bose , Jude Rivers , Jayanth Srinivasan
IPC分类号： G06F11/30
CPC分类号： G06F11/008
摘要： A system and method for projecting reliability to manage system functions includes an activity module which determines activity in the system. A reliability module interacts with the activity module to determine a reliability measurement for the module in real-time based upon the activity and measured operational quantities of the system. A management module manages actions of the system based upon the reliability measurement input from the reliability module. This may be to provide corrective action, to reallocate resources, increase reliability of the module, etc.
摘要翻译：用于投影可靠性以管理系统功能的系统和方法包括确定系统中的活动的活动模块。可靠性模块与活动模块进行交互，以基于系统的活动和测量的运行量实时地确定模块的可靠性测量。管理模块基于来自可靠性模块的可靠性测量输入来管理系统的动作。这可能是提供纠正措施，重新分配资源，增加模块的可靠性等。

106. 发明授权

US5805876A Method and system for reducing average branch resolution time and effective misprediction penalty in a processor 失效
标题翻译：减少处理器中平均分支分辨率时间和有效误判处罚的方法和系统
公开(公告)号：US5805876A
公开(公告)日：1998-09-08
申请号：US723171
申请日：1996-09-30
申请人： Pradip Bose , Kin Shing Chan , Hung Qui Le , Robert Eric Wasmuth
发明人： Pradip Bose , Kin Shing Chan , Hung Qui Le , Robert Eric Wasmuth
IPC分类号： G06F9/38
CPC分类号： G06F9/3804 , G06F9/3844 , G06F9/3861
摘要： Logic circuitry provides a fast resolution of conditional branch instructions in a high-performance superscalar processor. The logic circuitry facilities early (fast) resolution of a subset of conditional branches located within the first position of the primary instruction buffer within the processor enabling the overall branch processing logic to bypass history table-based prediction logic for such branches without crossing the cycle boundary. Thus, penalties associated with possible mispredictions for this subset of conditional branches are avoided.
摘要翻译：逻辑电路提供了高性能超标量处理器中条件分支指令的快速分辨率。逻辑电路设备处理位于处理器内的主指令缓冲器的第一位置内的条件分支的子集的早（快）分辨率，使得整个分支处理逻辑能够绕过这样的分支的历史表格预测逻辑，而不会跨越周期边界。因此，避免了与该子集条件分支的可能的错误预测相关的惩罚。

107. 发明授权

US08595731B2 Low overhead dynamic thermal management in many-core cluster architecture 失效
标题翻译：多核心集群架构中的低开销动态热管理
公开(公告)号：US08595731B2
公开(公告)日：2013-11-26
申请号：US12698545
申请日：2010-02-02
申请人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F9/46 , G06F9/44
CPC分类号： G06F9/46
摘要： A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution.
摘要翻译：半导体芯片包括多个多芯簇，每个多核簇包括多个核和集群控制器单元。每个集群控制器单元被配置为控制它所属的多核集群内的线程分配。集群控制器单元监视在多核集群内的多个核心中测量的各种参数，以估计在核心中运行的每个线程的计算需求。集群控制器单元可以基于线程的估计的计算需求来重新分配多核集群内的线程，并将信号发送到控制半导体芯片上的线程分配的上级软件管理器。当通过在多核心集群内的线程进行混洗，无法实现线程分配的可接受解决方案时，集群控制器单元也可能会报告无法解决线程分配给上级软件管理器以请求系统级解决方案。

108. 发明申请

US20110191776A1 LOW OVERHEAD DYNAMIC THERMAL MANAGEMENT IN MANY-CORE CLUSTER ARCHITECTURE 失效
标题翻译：多个核心集群架构中的低层动态热管理
公开(公告)号：US20110191776A1
公开(公告)日：2011-08-04
申请号：US12698545
申请日：2010-02-02
申请人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
发明人： Pradip Bose , Philip G. Emma , Eren Kursun , Jude A. Rivers
IPC分类号： G06F9/46
CPC分类号： G06F9/46
摘要： A semiconductor chip includes a plurality of multi-core clusters each including a plurality of cores and a cluster controller unit. Each cluster controller unit is configured to control thread assignment within the multi-core cluster to which it belongs. The cluster controller unit monitors various parameters measured in the plurality of cores within the multi-core cluster to estimate the computational demand of each thread that runs in the cores. The cluster controller unit may reassign the threads within the multi-core cluster based on the estimated computational demand of the threads and transmit a signal to an upper-level software manager that controls the thread assignment across the semiconductor chip. When an acceptable solution to thread assignment cannot be achieved by shuffling of threads within the multi-core cluster, the cluster controller unit may also report inability to solve thread assignment to the upper-level software manager to request a system level solution.
摘要翻译：半导体芯片包括多个多芯簇，每个多核簇包括多个核和集群控制器单元。每个集群控制器单元被配置为控制它所属的多核集群内的线程分配。集群控制器单元监视在多核集群内的多个核心中测量的各种参数，以估计在核心中运行的每个线程的计算需求。集群控制器单元可以基于线程的估计的计算需求来重新分配多核集群内的线程，并将信号发送到控制半导体芯片上的线程分配的上级软件管理器。当通过在多核心集群内的线程进行混洗，无法实现线程分配的可接受解决方案时，集群控制器单元也可能会报告无法解决线程分配给上级软件管理器以请求系统级解决方案。

109. 发明授权

US07685457B2 Interlocked synchronous pipeline clock gating 失效
标题翻译：联锁同步管道时钟门控
公开(公告)号：US07685457B2
公开(公告)日：2010-03-23
申请号：US11846847
申请日：2007-08-29
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： An integrated circuit including a pipeline and a method of operating the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种包括管道的集成电路和操作管道的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

110. 发明授权

US07475227B2 Method of stalling one or more stages in an interlocked synchronous pipeline 有权
标题翻译：在联锁同步管道中停止一个或多个阶段的方法
公开(公告)号：US07475227B2
公开(公告)日：2009-01-06
申请号：US11375989
申请日：2006-03-14
申请人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
发明人： Hans M. Jacobson , Prabhakar N. Kudva , Pradip Bose , Peter W. Cook , Stanley E. Schuster
IPC分类号： G06F9/30 , H04L5/00
CPC分类号： G06F1/3203 , G06F1/3237 , G06F1/324 , G06F1/3275 , G06F9/3869 , G06F9/3871 , Y02D10/126 , Y02D10/128 , Y02D10/14
摘要： A method of operating an integrated circuit including a pipeline and a method of stalling stages in the pipeline. Each stage of the pipeline is triggered by one or more triggering events and are individually, and selectively, stalled by a stall signal. For each stage a stall signal, delayed with respect to the stall signal of a downstream stage, is generated and used to select whether the pipeline stage in question is triggered. A data valid signal propagating with valid data adds further selection, such that only stages with valid data are stalled.
摘要翻译：一种操作包括流水线的集成电路的方法和在管线中停止级的方法。流水线的每个阶段由一个或多个触发事件触发，并且由失速信号单独且有选择地停止。对于每个阶段，产生相对于下游级的失速信号延迟的失速信号，并用于选择是否触发所讨论的流水线级。用有效数据传播的数据有效信号增加了进一步的选择，使得仅有有效数据的阶段停滞。

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