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    • 102. 发明授权
    • Method and apparatus for latching data around a logical data processor
    • 用于在逻辑数据处理器周围锁存数据的方法和装置
    • US5268596A
    • 1993-12-07
    • US791806
    • 1991-11-13
    • Masayuki Hata
    • Masayuki Hata
    • G06F13/42H03K3/012H03K3/037H03K19/017
    • H03K3/012H03K3/037
    • A control method for a data processing circuit which controls the timing of two clocks which independently control data latch circuits connected respectively with an input side and an output side of a logic circuit. The two clocks are held at a level which allows both data latch circuits to sample an input signal for a predetermined period. A data latch circuit comprises a first gate controlling whether or not an input signal is conducted to the logic circuit, an input end of a buffer circuit for latching the data signal and an output end of a second gate which causes an output of the buffer circuit to pass to an output end of the first gate, and a data processing circuit capable of sampling data, logically processing it, latching the result of the processing, and outputting it in one clock cycle, by interposing a logic circuit between the aforementioned two data latch circuits.
    • 一种用于控制独立地控制分别与逻辑电路的输入侧和输出侧连接的数据锁存电路的两个时钟的定时的数据处理电路的控制方法。 两个时钟保持在允许数据锁存电路在预定时间段内对输入信号进行采样的电平。 数据锁存电路包括控制输入信号是否传导到逻辑电路的第一门,用于锁存数据信号的缓冲电路的输入端和引起缓冲电路输出的第二门的输出端 传送到第一门的输出端,以及能够对数据进行采样,逻辑处理,锁存处理结果并在一个时钟周期内输出的数据处理电路,通过在上述两个数据之间插入逻辑电路 锁存电路。